極寬捕獲範圍的一位元取樣數位鎖相迴路

Abstract

在此篇論文中，我們提出具有極寬捕獲範圍的一位元取樣數位鎖相迴路。該數位鎖相迴路主要經由兩個步驟達成極寬捕獲範圍：一、資訊蒐集：進行多次的相位差偵測，將偵測到的平均相位值結合數位電路的特性，可迅速將數位振盪器的頻率逼近輸入訊號頻率。二、頻率徵調：利用傳統鎖相迴路的概念，將數位振盪器的頻率微調以鎖住輸入訊號頻率。 此外，我們將捕獲範圍分成：低頻、中頻以及高頻三個頻段，並個別給予不同的關鍵參數。依循以上步驟，我們實現極寬捕獲範圍的目標。由電腦模擬的結果顯示，在無雜訊干擾的環境中，自然頻率為10K Hz的一位元取樣數位鎖相迴路，可以達到的捕獲範圍為50 Hz ~ 10K Hz，此捕獲範圍為自然頻率的99.5%。

In this thesis, we propose the idea of one bit quantized digital phase-locked loop (PLL) with ultra-wide capture range. To achieve the goal, we devise two steps: 1. Information collection: we estimate the phase difference many times and average the results to obtain an accurate phase estimation. Combining the accurate estimation and the feature of digital PLL, we transfer the output frequency of numerically-controlled oscillator (NCO) to around the input signal frequency. 2. Fine frequency adjustment: based on the concept of phase locking, we slightly adjust the NCO output frequency until the system is locked. In addition, we separate the capture range into lower frequency, middle frequency and higher frequency ranges. Depending on the frequency range, we change some key factors in order to achieve phase locking over a wide frequency range. As a result, we can realize a digital PLL with ultra-wide capture range. From the simulation results, we can lock input frequency whose range is from 50 Hz to 10K Hz in noiseless environment, with an initial NCO natural frequency of 10K Hz. The system achieves almost 99.5% capture range of the natural frequency.