2.4-GHz低功率接收機與應用於60-GHz發射機之CMOS電路

Abstract

本篇論文設計並實現適用於無線個人區域網路的射頻積體電路。主要會依頻段分成兩大部份：第一部份針對現今較為成熟的ISM band，討論並比較各種低功率的技術，再實現兩種不同的2.4-GHz低功率接收機。第二部份則是實現出適用於60-GHz頻段的高品質元件電路。 論文首先會對於各種低功率的技術作研究，並且探究常見於直接降頻接收機的被動混頻器，其顫動雜訊的成因。再利用TSMC 0.18-贡m CMOS製程來實現一個結合被動混頻器的2.4-GHz低功率接收機，以及結合次臨界導通偏壓技術的2.4-GHz低功率接收機。 高頻電路的部份，利用TSMC 0.13-贡m CMOS製程，實現各種不同架構的60-GHz次諧波升頻混波器，並提出變壓器形式的巴倫來作輸出結合。為了提供良好的30-GHz本地震盪訊號源，還設計了一個結合三線耦合器的正交相位振盪器，可達到0.6V低壓操作，功率消耗7.6mW，且FoM為-203.6dBc/Hz。

In this thesis, the radios which are suitable for Wireless Personal Area Network (WPAN) applications are designed and implemented. The thesis consists of two parts. The first part focuses on studying various low-power techniques and realizes two different 2.4-GHz low-power receivers. The second part implements high quality component circuits which are suitable for 60-GHz band applications. First, we study different low-power techniques. Because the passive mixer is a common component of a direct-conversion receiver, we also investigate the flicker noise of passive mixers. Then, we implement a 2.4-GHz low-power receiver with passive mixers, and a 2.4-GHz low-power receiver with subthreshold biasing technique. Both chips are implemented in TSMC 0.18-um CMOS technology. Second, we implement different types of 60-GHz sub-harmonic upconverters in TSMC 0.13-um CMOS technology, and propose transformer-type balun to combine RF signal. In order to provide good LO source, we design a QVCO using three-line coupler. This QVCO operates at 0.6V, and consumes 7.6mW. And the FoM is -203.6dBc/Hz.