奈米級靜態隨機存取記憶體之特性擾動及其壓抑技術

Abstract

隨著半導體元件的微縮化，各種製程變異對元件的電特性造成重大影響。當互補式金氧半導體元件(CMOS)縮小至奈米等級，臨界電壓(Vth)擾動將更為顯著，此種擾動不只影響元件，更使得在設計超大型積體電路時，對於良率、雜訊邊界、穩定度、以及可靠度的控制更加困難。 在此論文中，吾人使用原子層級之三維度元件-電路耦合模擬技術，研究本質參數擾動在通道長度16奈米之平面場效電晶體(MOSFET)所組成之靜態隨機存取記憶體(SRAM)中引起的特性擾動。對於單元比率(Cell Ratio)為一的六電晶體(6T)靜態隨機存取記憶體，其靜態雜訊邊界(SNM)為20毫伏特，高達80%的靜態雜訊邊界擾動(σSNM)將無法保證此電路能正常操作。因此，在本論文中提出了元件及電路觀點的改善及擾動壓抑方法，實際模擬並驗證其特性。從電路的觀點，八電晶體(8T)靜態隨機存取記憶體架構在同樣的臨界電壓下，其靜態雜訊邊界提高至233毫伏特，而靜態雜訊邊界擾動也降低至22毫伏特(約為9.5%的擾動)，但和原六電晶體靜態隨機存取記憶體相比，多出了30%的晶片面積消耗。為了防止面積的增加，使用了絕緣層上矽(SOI)鰭式電晶體(FinFET)來取代六電晶體靜態隨機存取記憶體中的平面場效電晶體，在此元件觀點的改善下，其靜態雜訊邊界為125毫伏特，擾動亦被大幅壓抑至6.8毫伏特(約5.3%)。雖然八電晶體架構能夠提供最大的靜態雜訊邊界，並且在現階段而言可以滿足需求，但為了防止晶片面積的增加，以及壓抑隨著元件微縮化日趨嚴重的本質參數擾動影響，使用由絕緣層上矽鰭式電晶體構成的靜態隨機存取記憶體將更為有效。 總之，本研究已透過等效原子層級暨量子傳輸方程的大尺度統計運算方法發展之三維度元件-電路耦合模擬技術，來探討靜態隨機存取記憶體電路之特性擾動，並提供元件及電路觀點的改善壓抑方法，期待能對將來記憶體的技術發展有所助益。

As the dimension of complementary metal-oxide-semiconductor (CMOS) devices shrunk into sub-65nm scale, the threshold voltage Vth fluctuation is pronounced and becomes crucial for the design window, yield, noise margin, stability, and reliability of ultra large-scale integration circuits. Various randomness effects resulted from the random nature of manufacturing process have induced significant fluctuations of electrical characteristics in nanometer scale (nanoscale) devices and circuits. In this thesis, a three-dimensional “atomistic” coupled device-circuit simulation is intensively performed to investigate the impact of intrinsic parameter fluctuations on 16-nm-gate planar metal-oxide-semiconductor field-effect-transistor (MOSFET) static random access memory (SRAM) cells. For device with 140 mV threshold voltage, the static noise margin (SNM) of 6T SRAM with unitary cell ratio is 20 mV with 80% normalized SNM fluctuation (σSNM), which may not ensure correct operation of circuits. Thus, improvement and suppression approaches based on the circuit and device viewpoints are implemented to examine the associated characteristics in 16-nm-gate SRAM cells. From the circuit viewpoint, an 8T planar SRAM architecture is explored. Compared with the conventional 6T SRAM, under the same Vth = 140 mV, the SNM is enlarged to 233 mV and the SNM is reduced to 22 mV (around 9.5% normalized SNM) at a cost of 30% extra chip area. To prevent the increase of chip area, silicon-on-insulator fin-type field-effect-transistors (SOI FinFETs) replaced the planar MOSFETs in 6T SRAM is further examined. The SNM of 6T SOI FinFETs SRAM is 125 mV and the normalized σSNM is suppressed significantly to 5.3% (6.8 mV in σSNM). The 8T SRAM architecture can provide largest SNM and is promising in near future design; however, to prevent the increase of chip area and suppress the intrinsic parameter fluctuations, development of fabrication for SOI FinFET SRAM is crucial for sub-22nm technology.