具有增強之迴轉率並有高穩定範圍與低功率損耗之低壓降線性穩壓器

Abstract

本研究致力於實現不需負載電容和快速暫態切換特性之低壓降線性穩壓器(LDO Regulator)。在此論文中，提出兩個全新的增強式迴轉率架構於穩壓器電路，使系統晶片(System on a Chip，簡稱SoC)或可攜式產品的電源管理系統有效解決晶片外部大體積電容的問題。 首先，我們必需先了解，要使迴轉率增加最直接的方法就是提高偏壓電流源的電流，但提高偏壓電流相對會造成較大的功率損耗，因此我們在第一顆晶片設計上，設計了具有暫態推挽式偏壓且無輸出電容之低壓降穩壓器，當輸出端電壓有較大幅度變化時，才會增加偏壓電流源的電流以達到快速的恢復輸出端電壓，並且在此電路中加上一個動態偏壓電路，用來加快暫態的效應。而第二顆晶片設計，除了提昇迴轉率之外，特別設計新型雙級誤差放大器來提高開迴路增益，使負載穩壓及線上穩壓都有較好的表現。同時也採用簡單的電流鏡，動態增加偏壓源電流，以增加電路迴轉率，改善電路暫態效應。 我們所設計的這兩個低壓降線性穩壓器從負載電流0mA至100mA範圍內，在輸出端沒有接任何負載電容的情況下仍然可以提供高穩定度。所設計的系統輸出電壓為1.1V，最大可承受的負載電流為100mA。本論文所呈現之晶片都是使用台積電所提供之0.18微米1P6M及0.35微米2P4M的標準互補式金氧半製程來作設計。

This research focuses on the realization of capacitorless and fast transient low dropout (LDO) linear regulator. We present two slew-rate enhancement architectures for new LDO circuits. The thesis provides a solution for power management system of portable devices. It can also be embedded in SoC (System on a Chip) to fully remove bulky external capacitors. The instant way to raise the slew rate is to raise the bias current, which, however, causes higher power consumption. Therefore, we design the first chip of the capacitorless low-dropout voltage regulator with fast transient through push-pull biasing. When the output voltage has larger variation, it will increase the bias current to pull the output voltage back to the original value quickly. Moreover, we design a dynamic bias circuit to fasten the transient response. As for the second chip, we not only raise its slew rate, but also design a new type of two-stage error amplifier to increase DC loop gain and enhance load regulation and line regulation performance efficiency. Meanwhile, we use simple current mirrors to raise bias current to dynamically increase slew rates and improve transient responses. These two low dropout regulators can provide loading current from 0mA to 100mA, and maintain the stable status even without load capacitor. The both systems have an output voltage of 1.1 V and a maximum current capability of 100 mA. The proposed chips were fabricated by standard TSMC 0.18 μm 1P6M and 0.35 μm 2P4M CMOS processes, respectively.