Scalable short-open-interconnect S-Parameter de-embedding method for on-wafer microwave characterization of silicon MOSFETs

Abstract

In this paper, we propose an accurate and scalable S-parameter de-embedding method for RF/microwave on-wafer characterization of silicon MOSFETs. Based on cascade configurations, this method utilizes planar open, short, and thru standards to estimate the effects of surrounding parasitic networks on a MOS transistor. The bulk-shielded open and short standards are used to simulate and de-embed the probe-pad parasitics. The thru standard are used to extract the interconnect parameters for subtracting the interconnect parasitics in gate and drain terminals of the MOSFET. To further eliminate the parasitics of dangling leg in source terminal of the MOSFET, we also introduce the microwave and multi-port network analysis to accomplish the two-port-to-three-port transformation for S-parameters. The MOSFET and its corresponding de-embedding standards were fabricated in a standard CMOS process and characterized up to 40 GHz. The scalability of the open, short, and thru standards is demonstrated and the performance of the proposed de-embedding procedure is validated by comparison with several de-embedding techniques.