多晶矽薄膜電晶體在關閉區閘極脈衝電壓操作下的劣化行為研究

Abstract

多晶矽薄膜電晶體(poly-Si TFTs)在顯示器中已被廣泛地使用，在三階驅動的應用上，由於電路結構的關係，會使得元件操作於閘極關閉區(Gate AC OFF)中；另外在更廣泛被採用在主動式矩陣(Active matrix)驅動的面板上，我們發現每個畫素上的電晶體，會長時間地處於汲極信號的關閉區操作情況。 在本論文中，主要是針對閘極關閉區的元件劣化行為做進一步的探討。並藉由和其他劣化條件的交叉比較。發現劣化原因主要是來自於靠近汲極的大電場造成的劣化行為，這些劣化條件之間的差異，主要是在劣化電流的來源與大小不同。並且由於電流大小的差異，造成劣化的程度也會不一樣。 最後，為了了解在動態操作下元件的劣化行為的細節，我們考慮了許多不同的波形條件，並且探討他們與劣化趨勢之間的相依性。我們試著使用RC充放電的概念去解釋這些行為，並設計了幾個小實驗確認我們的想法。 藉由這些新發現，期望以後在設計元件或是驅動電路上，能夠把這些劣化行為考慮進去，以增加元件的可靠度。

Poly silicon TFTs are widely used in LCD panels. In the storage-on-gate array structures, each pixel TFT would be under Gate AC Off region operation. In active matrix addressing method, we found that each TFT is most of time under drain off region dynamic operation. In this thesis, we want to focus on the degradation mechanism while devices are operated in off region. By the similar behavior of other three stress conditions, we found the degradation behavior is from the large electric field near drain electrode. In addition, the degradation rate is also from the amount of stress current. In general, degradation rate of on region stress is much larger than off region stress because of the on current is larger then leakage current under off region operation. In order to know the detail of the device under dynamical operation, we then consider the waveform parameters and its dependence with the degradation rate. However, we try use the concept of RC charge and discharge model to explain the waveform parameters dependence. By this study, we are expected designer could consider these degradation behavior and do the drain engineering to enhance device reliability.