多晶矽薄膜電晶體的空間與時間變動性探討

Abstract

本論文探討多晶矽薄膜電晶體的在空間與時間上的特性變動。本論文雖然主要動機出發於主動式顯示器電路應用，但其結果則可擴大應用於顯示器以外的領域。本文首先討論在量產線上的元件特性變動，發現元件的變動特性除了有很嚴重變動範圍之外，其變動行為亦沒有模型能夠精確描述；這將在設計多晶矽薄膜電晶體電路時造成很大的問題。因此我們先參考在在金-氧-半導體電晶體(MOSFETs)結構中對於元件變動的討論，並且以類似的方式針對薄膜電晶體的變動性提出可能的變動因素。由此我們提出一”枕木型”布局方式並對此布局內的元件參數進行統計。此枕木型布局方式的特色是元件間的距離盡可能的縮到最小並且在此最小間距內，兩相鄰元件間的長距離變動(long-range variation)可以大幅降低。所量測到的元件參數呈現非對稱且不集中的分佈，與先前一般所預測的高斯分佈有明顯落差。利用電子學裡的小信號想法，我們可以將兩相鄰元件間的長距離變動與微觀變動(micro variation) 區分開，並可以進一步探討元件間的微觀變動模型。對元件的起始電壓與載子遷移率而言，N型與 P型元件其微觀變動行為均呈現較集中與對稱的行為。我們提出兩個數學式以精確描述其微觀變動的參數分佈，並根據此兩模型探討元件的變動行為在數位與類比電路上造成的影響。此外，我們亦利用此模型預測元件在不同元件尺寸下的變動行為。在論文研究方向上，利用枕木型元件布局可使元件的變動範圍大幅減小，以起始電壓為例，其標準差由0.5 V 縮減至0.03 V，這將有助於我們之後的元件時間變動性的討論，不會因元件空間上的變動行為而遮蓋住其在時間上的變動行為。 接下來我們討論元件在時間上的變動性。此處，元件的時間變動性可以單純的理解為其在直流與交流下的可靠度行為，並將於不同的章節裡個別討論。對於元件在直流操作下的可靠度行為，我們首先回顧元件在兩大劣化機制下，亦即為熱載子效應與自發熱效應，先前文獻已經發表的劣化行為。雖然已有很多文獻探討元件在這兩大劣化行為下所產生的元件特性改變，關於這兩個操作條件下元件的電容行為部份卻只有零星的文獻。我們討論在這兩個劣化行為下元件的電容特性變化，發現元件模擬軟體並不能很完整的描述元件的電容特性在不同量測頻率下的行為。因此我們採用另一個方法，利用相對較易取得的元件電流特性推論元件的電容特性，提出一由閘極界電層電容與通道電阻所組成的元件模型，利用探討元件的阻抗中的電容項與電阻項，我們定義一個特別的點PC以幫助我們利用元件的電流特性去探討其電容特性。由於阻抗的電容項與量測頻率有關，PC的位置亦與量測頻率有關。利用這個方式，我們探討元件在兩個主要劣化條件下的行為，同時也提出在這兩個操作條件下，元件在操作後的電路模型。對於兩個特別的電容特性在關閉區的行為，亦即N型元件在自發熱操作條件後與P型元件在熱載子操作條件後的現象，將會有一特別的討論。 接下來我們探討元件在閘極交流操作下的劣化行為。由應用端出發，我們發現元件在液晶顯示器面板內絕大部分時間處於閘極關閉區而其集極則持續給予交流訊號。然而，關於這個操作條件卻沒有任何已知的文獻探討其劣化行為。比較其閘極與源極電壓差以及閘極與集極電壓差，我們可以將其操作條件類比為閘極關閉區內的交流操作，而其源極與集極則均接地。N型元件在這樣的操作條件下，其電流特性出現了載子遷移率的下降，而電容則有扭曲(Distortion)的現象。對P型元件，其電流特性則出現了載子遷移率的上升，而電容則在關閉區出現異常的上昇。我們亦探討元件的劣化行為與閘極電壓的參數，以及其電壓範圍、頻率與工作週期(Duty cycle)的關聯。然而，由於其閘極電壓均低於其起始電壓，在通道裡應該沒有通道載子，也因此這個劣化行為無法利用先前由Uraoka所提出的模型解釋。在此我們依然使用前文所使用的元件模型，並且同樣討論元件在此操作條件下的阻抗行為。我們推論在此操作情況下元件的源極與集極接面將會有很大的電場，並進一步造成元件的劣化。然而，這樣的推論無法被直接驗證因為我們並沒辦法直接探測元件內的電壓分佈，因此我們使用一稱作gated p-i-n測試結構，其結構與TFT相似但其一端源極與集極的參雜經過更改，使其橫向結構類似一p-i-n元件。採用這種結構的特色是這樣的元件擁有和與TFT相似的結構，但其通道內的電壓可以由一端的接面控制，進而可以讓其另一接面上形成大電場。這樣，經由比較交流操作後的TFT與直流操作後的gated-p-i-n元件，我們先前所提出的理論獲得證實－處於很大逆向偏壓源極與集極接面的劣化是閘極關閉區下交流操作的劣化主因。關於N型與P型元件的不同劣化行為亦有深入討論。此外，亦比較了幾個相似的劣化條件，發現不論載子的來源來自於導通區的集極電流，或是關閉區的漏電流，抑或是由導通區切向關閉區時，由通道區被空乏掉的載子，一但接面上有大電場的產生，均會出現類似熱載子效應的劣化行為；由另一角度來看，其亦可被總結為一廣義的熱載子效應。總結而言，本文所提出的模型與其劣化模型將會為元件的時間變動特性提供有用的資訊，也可幫助評估元件的時間變動行為。

This work focuses on the variation behavior of poly-Si TFTs both spatially and temporally. This work is mainly enlightened from, but not limited to, the display electronics. First the spatial variation of the devices is studied for the devices from the mass production line. The serious variation behavior and no description nor trend for the device variation makes it rather difficult for designers to develop the circuits composed of poly-Si TFTs. Thus we referred to the cases in MOSFETs and analogically proposed factors for the variation behavior for poly-Si TFTs. Based on the idea, the special layout called crosstie layout is proposed, measured and the device parameters are extracted and statistically summarized. The feature of the crosstie layout is that the devices are located as close as possible and in such case the long-range variation can be greatly reduced for the two adjacent devices. The device parameters show apparent asymmetric and non-centered distribution, which is much different from the usual Gaussian distribution assumption. A method enlightened from the electronics is proposed to decouple the long-range and micro variation and by finding the difference between the adjacent devices the true micro variation profile can be examined. The micro variation behaviors for the threshold voltage and mobility are found to be more centered and symmetric for both n-type and p-type devices. Two equations are proposed to well fit the micro variation and also based on the models the effects of device variation on the analog and digital circuits are simulated and discussed. In addition, based on the models, the projected device variation behavior for devices with different device dimension is also provided. By utilizing the crosstie layout, the variation behavior of the devices is greatly reduced, take the threshold voltage for instance, from 0.5 V to 0.03 V. The reduced variation also facilitates the following study of temporal variation, in which the effect of spatial variation can be greatly relieved and not to cover the effect of temporal variation. Then we focus on the temporal variation of poly-Si TFTs under various operation conditions. Here the temporal variation can simply correspond to the reliability issue under DC and AC operation, which would be respectively discussed in the separate chapters. For the DC operation section, we first review the two main degradation mechanisms for the poly-Si TFTs under DC operation, namely the hot carrier effect and the self heating effect. Though there have been so many papers on the device degradation behavior under these two stress conditions, there are very few papers about their capacitance behavior. We study the C-V behavior for the device after the two stress conditions and find that the simulation tool may be incomplete in properly describing the frequency dependence in the C-V curves. Thus we use another approach to infer the C-V curves from the readily-accessible I-V curves. Based on the proposed model composed of the gate insulator capacitance and channel resistance, we compare the magnitude of the capacitance term and the resistance term for the device’s impedance and the critical point called PC is found to help distinguish the ON region and the OFF region in the C-V curves inferred from the I-V curves. Since the capacitance term is dependent on the measuring frequency, the position of the point PC also changes with the measuring frequency. Following the same manner, the C-V behavior for the device after the two stress conditions are examined and the corresponding circuit elements, possibly the capacitance or the resistance, are proposed respectively. Special discussion would be given on the capacitance behaviors for the n-type device after self-heating stress and the p-type after hot carrier stress since they both somehow show the increase of the capacitance for the lower gate voltage in C-V curves. Next we study the reliability behavior for the device under gate dynamic operation. Started from the application, we find that in TFT-LCD applications the TFTs in the pixels mostly stay in the gate turned-off region with the drain signal dynamically toggling. However, there is almost no study of the reliability behavior on such operation condition. We consider the gate-to-source voltage difference VGS and the gate-to-drain voltage difference VGD and analogically study the reliability behavior for the gate voltage dynamically toggling in the OFF region while the source and drain electrodes are both grounded. The device shows mobility decrease in the I-V curves and shift as well as distortion in its C-V curves for the stressed n-type device, while for the p-type device the mobility increases and the OFF current decreases after stress. The dependency for the device degradation on the pulse parameters, namely the pulse range, the frequency and the duty ratio of the applied signal, is also studied. However, since the pulse voltage is all kept below its threshold voltage, there should be no channel carrier induced beneath the gate electrode and thus the degradation behavior could not be explained by the model proposed previously by Uraoka. At this point we resort to the circuit model again and one more time we discuss the impedance under such stress condition. It is then inferred that under the gate AC operation the channel resistance and the large electric field across the junctions could be the main degraded region. Nevertheless, such inference is hard to probe and we use another test structure named the gated p-i-n device, in which the device has the similar structure to TFTs but one side of the doping is changed to make the device laterally resemble the p-i-n diodes. The feature for adopting such gated p-i-n device is that this device has the similar structure to the TFTs while the channel voltage can be set from one side of the electrodes. Thus, this enables us the capability of forming large electric field across one junction to simulate the condition of gate AC OFF region stress for poly-Si TFTs. Then, by examining the capacitance curves of the AC-stressed TFTs and the DC-stressed gated p-i-n devices after stress, the aforementioned mechanism is verified. The degradation in junction with the large electric field on it is thus found to be responsible for the degradation of gate dynamic operation in the OFF region and the discussion for the different behaviors for the n-type device and p-type device is also provided. Also the reliability behaviors under several other stress conditions are discussed. It is found that, no matter what the carrier source may be the inversion channel carriers, the leakage current or even the inversion channel carriers swept because the gate pulse is to be turned-off, once the large electric filed is across the junction, the carriers would more or less become the hot carrier and result in the similar degradation behavior. In other words, they can be categorized as the “generalized hot carrier effect.” To summarize, the finding of the mechanism as well as the proposed circuit model should provide useful information for the understanding and evaluation of the temporal variation for poly-Si TFTs.