奈米線薄膜電晶體元件之研究

Abstract

在博士論文中，我們針對新穎結構應用於薄膜電晶體元件之研究: 首先，在鰭式通道電晶體在近年來被廣泛研究之際，我們利用低成本且簡單的方法製備類鰭式通道薄膜電晶體結構；藉著氮化矽/二氧化層雙層結構，使得此一元件製作過程無需任何先進的微影系統而能得到一具有雙閘極垂直通道結構高效能薄膜電晶體；其中二氧化層蝕刻輪廓好壞將直接影響鰭式通道之外型並影響後續電性。類鰭式通道高度約為200奈米而通道寬度約為45奈米並在無電漿輔助處理之下獲得相當好的元件特性，其中次臨界擺幅達到約145 mV/dec，並在經過電漿處理過後進一步將次臨界擺幅降低到約132 mV/dec，如此低成本、簡單且具有優異元件特性的矽奈米通道元件相當適合應用於三維積體電路及系統整合之範疇。 再者，新穎的閘極環繞式多晶矽奈米通道結構搭配抬昇式源極/汲極之薄膜電晶體在薄膜電晶體的範疇中首度提出與驗證；利用氮化矽/二氧化層/氮化矽三明治結構，有效將多晶矽奈米通道微縮至十奈米以下而無需先進的微影系統，並且具有相當勻稱之橢圓外形;此外，在閘極結構上利用栓塞形式可有效於後續製程中保護奈米線通道，此在多晶矽奈米通道薄膜電晶體的範疇中亦是第一次被提出。如此微縮且勻稱的矽奈米通道，促其元件特性在沒有氫相關電漿處理下有相當程度的提升;這些提升包含了具有相當低的臨界電壓約0.234V、大幅降低操作之閘極電壓至3V、陡峭的次臨界擺幅約99 mV/dec及高開關電流比超過107。除此之外，此元件之驅動電流在通道寬度的歸一化下達到198 µA/µm；並在汲極電壓 1V下僅有0. 3 nA/□m 的漏電流。以上元件特性的改善與提升可以歸因於閘極控制能力大大的增加，而此增加進一步的使汲極誘發能障下降的效應被有效的抑制並在驅動電流的量測中幾乎可以忽略浮接基體效應。 此外，，我們首次針對閘極環繞式多晶矽奈米通道結構搭配抬昇式源極/汲極之薄膜電晶體搭配溫度的變換進行特性與可靠度的觀察與探討，在溫度升高的過程中，具有10奈米以下之奈米線通道元件具有相當穩定的電流特性與較好的可靠度。因此，如此具有優異元件特性的矽奈米通道元件相當適合應用於三維積體電路及系統整合之範疇。 最後，我們結合閘極環繞式多晶矽奈米通道結構與抬昇式源極/汲極，結合栓塞形式閘極並搭配臨場摻雜之技術，發展無接面式奈米線通道薄膜電晶體元件；在沒有氫相關電漿處理下亦有相當優異的特性;包含了具有相當陡峭的次臨界擺幅約80 mV/dec及開關電流比超過107。當整個奈米線通道充滿均勻摻雜時，通道與源極/汲極將不會有濃度的梯度變化所造成的擴散，因此製程的變異性及後續熱製程造成的擴散問題有效降低，預期此無接面式奈米線通道薄膜電晶體元件於閘極長度在持續微縮過程中將更具競爭力。

First, we demonstrate poly-Si thin film transistors with novel L-Fin channels (LFin-TFTs) without the use of advanced lithographic tools. Compared with general process of FinFETs, the LFin-TFTs processes are simpler and lower cost. We make the fin-like channel by TEOS dummy layer and TEOS spacer. The profile of L-Fin channel can be control from etching profile of TEOS dummy layer. The impact of profile of L-Fin channel is also consideration. In the conventional FinFETs or Fin TFTs processes, the thickness of fin are defined by advanced lithographic tools and sidewalls of fin channel are patterned by dry etching. The sidewall roughness is an important issue. In this work, the TEOS dummy layer and spacer can protect the sidewalls of L-Fin channel from dry etching steps. Furthermore, additional NH3 plasma treatment was adopted to effectively passivate the defects and interface states in LFin-TFTs. The well-behaved electric characteristics (low off-leakage currents, good S.S., improved DIBL, and high ION / IOFF) simultaneously achieved in the LFin-TFTs are the result of the multiple-gated L-Fin channel structure. These high- performance LFin-TFTs appear to be promising for future applications in SOP and 3-D IC. Then, a novel Gate-All-Around Nanowire Poly-Si TFTs with self-aligned corked gate Raised Source/Drain structure (Gate-All-Around Raised Source/Drain Nanowire Poly-Si TFTs, called GAA RSDNW-TFTs) are successfully demonstrated. The nanowire dimension is 7 nm × 12 nm. For the first time, a superior smooth elliptical shape is obtained in the category of the Poly-Si nanowire TFTs through the use of a novel fabricated process without advanced lithographic tools. The GAA RSDNW-TFTs exhibit a very low threshold voltage (VTH ~0.243V), low supply voltage (VG ~3V), steep subthreshold swing (S.S. ~ 99 mV/dec) and high ION/IOFF ratio>107 without hydrogen related plasma treatments. In addition, these GAA RSDNW devices have a high drive-current performance with IDSAT = 198 □A/□m (circumference-normalized) and off-current IOFF = 0. 3 nA/µm at supply voltage VD = 1 V. Furthermore, the DIBL of the GAA RSDNW-TFTs is well control. These improvements can be attributed the three-dimensional (3-D) gate controllability. Moreover, the variability of the main electrical parameters with the temperature dependence and the PBTI stress are small. A similar electrical characteristic is observed with number of channels. This combination of the GAA gate stacked structure, raised S/D, and sub-10-nm NW channel appears to be promising for SOP and future monolithic 3-D IC applications. Finally, a novel GAA Si NW TFTs with sub-5-nm Si NW and raised S/D structures with junctionless configuration is successfully demonstrated in this chapter. We propose and demonstrate a new type of transistor in which there are no junctions and no doping concentration gradients by the in-situ doped channel. A junctionless configuration is combined with nanowire, a corked gate (CG) structure and raised S/D to form the junctionless nanowire thin film transistors (JLNW-TFTs). These novel transistors exhibit steep S.S., low off state leakage current and improved driving current. Furthermore, the temperature dependence of the main electrical parameters of JLNW-TFTs and inversion mode thin film transistors is analyzed. JLNW-TFTs with gate-all-around structure exhibit only limited variation in threshold voltage with temperature dependence. In addition, thanks to good gate controllability, the variability of the main electrical parameters with temperature dependence is also small. Hence, this combination of GAA gate stacked structure, raised S/D, and sub-5-nm JLNW-TFTs appears to be promising for SOP and future monolithic 3-D IC applications.