DESIGN OF ALGORITHM-BASED FAULT-TOLERANT VLSI ARRAY PROCESSOR

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DC Field	Value	Language
dc.contributor.author	LIU, CM	en_US
dc.contributor.author	JEN, CW	en_US
dc.date.accessioned	2014-12-08T15:05:45Z	-
dc.date.available	2014-12-08T15:05:45Z	-
dc.date.issued	1989-11-01	en_US
dc.identifier.issn	0143-7062	en_US
dc.identifier.uri	http://hdl.handle.net/11536/4273	-
dc.language.iso	en_US	en_US
dc.title	DESIGN OF ALGORITHM-BASED FAULT-TOLERANT VLSI ARRAY PROCESSOR	en_US
dc.type	Article	en_US
dc.identifier.journal	IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES	en_US
dc.citation.volume	136	en_US
dc.citation.issue	6	en_US
dc.citation.spage	539	en_US
dc.citation.epage	547	en_US
dc.contributor.department	交大名義發表	zh_TW
dc.contributor.department	電控工程研究所	zh_TW
dc.contributor.department	National Chiao Tung University	en_US
dc.contributor.department	Institute of Electrical and Control Engineering	en_US
dc.identifier.wosnumber	WOS:A1989CB44300012	-
dc.citation.woscount	6	-
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