DESIGN OF ALGORITHM-BASED FAULT-TOLERANT VLSI ARRAY PROCESSOR

標題:	DESIGN OF ALGORITHM-BASED FAULT-TOLERANT VLSI ARRAY PROCESSOR
作者:	LIU, CM JEN, CW 交大名義發表電控工程研究所 National Chiao Tung University Institute of Electrical and Control Engineering
公開日期:	1-Nov-1989
URI:	http://hdl.handle.net/11536/4273
ISSN:	0143-7062
期刊:	IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES
Volume:	136
Issue:	6
起始頁:	539
結束頁:	547
Appears in Collections:	Articles

Files in This Item:

If it is a zip file, please download the file and unzip it, then open index.html in a browser to view the full text content.