标题: | 低电压互补式金氧半制程下可相容高工作电压之静电放电防护设计 High-Voltage-Tolerant ESD Protection Design in Low-Voltage CMOS Processes |
作者: | 张玮仁 Wei-Jen Chang 柯明道 Ming-Dou Ker 电子研究所 |
关键字: | 静电放电;二次崩溃电流;混合电压输入输出界面;低电压驱动双载子接面电晶体;可耐高工作电压之静电放电箝制电路;真空萤光显示器;高压P型矽控整流器;人体放电模式;机械放电模式;electrostatic discharge;secondary breakdown current;mixed-voltage I/O interfaces;low-voltage-triggered PNP;high-voltage-tolerant ESD clamp circuit;vacuum-fluorescent-display;high-voltage P-type silicon controlled rectifier;human-body-model;machine-model |
公开日期: | 2007 |
摘要: | 随着半导体制程的进步与发展,积体电路产品已经成为民生用品般地大量制造与使用,许多整合多功能的系统晶片(SoC)已经成为各电子公司的产品研发主力,电子产业也在这个领域有长足的进步与发展。但由于半导体制造技术的日新月异,使得积体电路对静电放电防护的能力下降很多,同时由于操作电压一直在下降,但是周边电路的电压却未随半导体制程的进步而降低,所以在扮演晶片输入输出媒介的混合电压界面(Mixed-Voltage I/O Interface)上将会产生许多问题,尤其在电子系统讯号整合上。因此要在此混合电压电路加上其静电放电保护电路,需要考量界面电压转换、混合电压界面间的漏电流 (Leakage Current)、混合电压界面电路的可靠度(Reliability)等问题。因此,在混合电压界面上,如何仔细评估这些问题进而设计出具有高的静电放电防护能力的电路将是当今以及未来积体电路设计上的重要课题,这个主题随着半导体制程进入 0.13微米 以及90奈米之后,对积体电路设计产业更加重要。另外,随着高压金氧半制程在面版驱动电路(LCD Driver ICs)、电源供应器(Power Supplies)、电源管理(Power Management),以及汽车电子(Automotive Electronics)等使用的普及化,对于使用在这些应用的输出端以及当作静电放电保护元件的高压电晶体来说,静电放电的可靠度问题将比在一般低压制程的元件来得严重,因此如何有效改善静电放电耐压能力,将是这些高压积体电路设计上很重要的课题,这个主题也随着这些产业应用上的多元化而更趋重要。所以本论文分别针对了混合电压界面电路以及高压金氧半制程应用上的限制与困难作讨论,并进一步设计出有效的静电放电防护电路以适用在各相关应用之积体电路晶片。 首先,本论文提出了一种新型的低电压驱动双载子接面电晶体(Low-Voltage-Triggered PNP, LVTPNP)来当作混合电压输入输出界面(Mixed-Voltage I/O Interfaces)之静电放电保护元件。此新型静电放电保护元件是在CMOS制程中寄生的双载子接面电晶体的N型井(N-Well)以及P型基板(P-Substrate)接面上,额外植入N型或是P型的扩散离子所构成,以降低N型井以及P型基板接面的崩溃电压,当输入电压比VDD高(Over-VDD)或比VSS低(Under-VSS)时,不会有漏电以及闸极氧化层的可靠度问题。在0.35微米互补式金氧半制程,已经验证了此低电压驱动双载子接面电晶体会比传统寄生的双载子接面电晶体的静电放电耐受程度来得高,而该元件的最佳化布局方式(Layout Style)也在0.35微米以及0.25微米互补式金氧半制程中验证来提升元件本身的静电放电耐受程度,经由实验证明,具有多指状(Multi-Finger)布局方式的元件静电放电耐受程度会比单指状(Single Finger)的要来得高。除此之外,在0.25微米制程的晶片验证下,具有多指状布局方式的低电压驱动双载子接面电晶体搭配电源间的静电放电箝制电路(Power-Rail ESD Clamp Circuit)成功地提升了非同步数位用户专线(Asymmetric Digital Subscriber Line, ADSL)输入级的静电放电耐受程度,此输入级的讯号界于5V到-1V之间,此电压同时超过了该IC之VDD(2.5V)和低过了该IC之VSS(0V)。 本论文研究的第二部分,为了提供有效的静电放电防护于1.2/2.5V混合电压输入输出界面,本论文提出了新型的静电放电保护架构并在0.13微米制程中成功验证,此架构同时利用了静电放电汇流排(ESD BUS)以及可耐高工作电压之静电放电箝制电路(High-Voltage-Tolerant ESD Clamp Circuit)来实现。当混合电压输入输出界面的焊垫(Pad)对VDD(或VSS)之间遭受静电轰击或是输入输出脚对脚(Pin-to-Pin)之间遭受静电轰击时,此静电放电保护架构都可以提供相对应的放电路径来避免内部电路遭受静电损坏。在此静电放电防护电路中,可耐高工作电压之静电放电箝制电路都是利用1.2V低压元件来实现,并可安全地在2.5V的电压偏压下工作而不会有闸极氧化层的可靠度问题。由实验可知,比起一般的堆叠式电晶体(Stacked-NMOS)而言,基板触发(Substrate Triggered)技术可以有效提升该可耐高工作电压之静电放电箝制电路的导通速度以及静电放电耐受程度。在堆叠式电晶体的元件尺寸为480um/0.2um的大小之下,1.2/2.5V的混合电压输入输出界面之人体放电模式静电放电耐压能力(HBM ESD levels)可以从原本的5kV增加到6.5kV;同时,机械放电模式静电放电耐压能力(MM ESD levels)可以从原本的275V增加到400V。 本论文研究的第三部份,为了提升应用在车用电子(Automotive Electronics)中的真空萤光显示器(Vacuum-Fluorescent-Display, VFD)驱动IC的静电放电耐受程度,本论文提出一种新型的静电放电保护的元件结构。此元件结构是在高压P型的金氧半电晶体(HVPMOS)的汲极当中植入一个N型离子布植来形成一个嵌入式高压P型矽控整流器(High-Voltage P-Type Silicon Controlled Rectifier, HVPSCR)路径,此结构只需要加入额外的N型离子局部布局面积即可实现。在0.5微米的互补式金氧半制程中,成功验证了具有此嵌入式高压P型矽控整流器的真空萤光显示器驱动积体电路的人体放电模式静电放电耐压能力可以从不到500V增加到8kV;同时,当元件尺寸为500um/2um、600um/2um以及800um/2um时,机械放电模式之静电放电耐压能力可以通过1100V、1300V以及1900V的静电测试。此外,此嵌入式高压P型矽控整流器的真空萤光显示器驱动积体电路可成功通过 □200mA的闩锁(Latchup)测试。 本论文研究的第四部分,观察到使用在输出端以及当作静电放电保护元件的高压电晶体,静电放电的可靠度问题比在一般制程的元件来得严重,因此本论文利用40-V金氧半制程对于不同元件结构以及汲极到闸极的距离(Layout Spacing from Drain to Polygate)做一深入探讨。实验结果成功验证了汲极下端没有植入的飘移掺杂(Drift Implant)布局的高压金氧半电晶体比起汲极下端有加入移掺杂的高压金氧半电晶体有较高的二次崩溃电流(Secondary Breakdown Current, It2)以及较好的静电放电防护能力。在所有元件结构当中,嵌入在高压N型的金氧半电晶体中的高压N型矽控整流器(HVNSCR)并在汲极下端移除了飘移掺杂的结构,具有最高的二次崩溃电流以及静电放电耐受度。此外,元件模拟技巧也成功地分析了有无飘移掺杂对于元件内电流分布的影响。 本论文分别针对了混合电压界面电路以及高压金氧半制程应用上的限制与困难作讨论,并进一步设计出有效的静电放电防护电路应用在各相关之积体电路晶片。本博士论文所提出电路已经有相对应的国际期刊与会议论文发表以及专利申请。 The scaling trend of the CMOS technology is toward the nanometer region to increase the speed and density of the transistors in integrated circuits. Due to the reliability issue, the power supply voltage is also decreased with the advanced technologies. However, in an electronic system, some circuits could be still operated at high voltage levels. If the circuits realized with low-voltage devices are operated at high voltage levels, the gate-oxide breakdown and leakage issues will occur. Therefore, for the CMOS integrated circuits (ICs) with the mixed-voltage I/O interfaces, the on-chip electrostatic discharge (ESD) protection circuits will meet more design constraints and difficulties. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths during normal circuit operating operation. During ESD stress condition, the on-chip ESD protection circuit should provide effective ESD protection for the internal circuits. In high-voltage CMOS technology, high-voltage transistors have been widely used for display driver ICs, power supplies, power management, and automotive electronics. The high-voltage MOSFET was often used as the ESD protection device in the high-voltage CMOS ICs, because it can work as both of output driver and ESD protection device simultaneously. With an ultra-high operating voltage, the ESD robustness of high-voltage MOSFET is quite weaker than that of low-voltage MOSFET. Hence, how to improve the ESD robustness of HV NMOS with a reasonable silicon area is indeed an important reliability issue in HV CMOS technology. In this thesis, some new ESD protection structures are proposed to improve ESD robustness of the high-voltage IC products fabricated in CMOS technology. To protect the mixed-voltage I/O interfaces for signals with voltage levels higher than VDD (over-VDD) and lower than VSS (under-VSS), ESD protection design with the low-voltage-triggered PNP (LVTPNP) device in CMOS technology is proposed. The LVTPNP is realized by inserting N+ or P+ diffusion across the junction between N-well and P-substrate of the PNP device. The LVTPNP devices with different structures have been investigated and compared in CMOS processes. The experimental results in a 0.35-um CMOS process have proven that the ESD level of the proposed LVTPNP is higher than that of the traditional PNP device. Furthermore, layout on LVTPNP device for ESD protection in mixed-voltage I/O interfaces is also optimized in this work. The experimental results verified in both 0.35-um and 0.25-um CMOS processes have proven that the ESD levels of the LVTPNP drawn in the multi-finger layout style are higher than that drawn in the single finger layout style. Moreover, one of the LVTPNP devices drawn with the multi-finger layout style has been used to successfully protect the input stage of an ADSL IC in a 0.25-um salicided CMOS process. To increase the system-on-chip ESD immunity of micro-electronic products against system-level ESD stress, the chip-level ESD/EMC protection design should be enhanced. Considering gate-oxide reliability, a new ESD protection scheme with ESD_BUS and high-voltage-tolerant ESD clamp circuit for 1.2/2.5 V mixed-voltage I/O interfaces is proposed in this chapter. The devices used in the high-voltage-tolerant ESD clamp circuit are all 1.2 V low-voltage NMOS/PMOS devices which can be safely operated under the 2.5 V bias conditions without suffering from the gate-oxide reliability issue. The four-mode (PS, NS, PD, and ND) ESD stresses on the mixed-voltage I/O pad and pin-to-pin ESD stresses can be effectively discharged by the proposed ESD protection scheme. The experimental results verified in a 0.13 um CMOS process have confirmed that the proposed new ESD protection scheme has high human-body-model (HBM) and machine-model (MM) ESD robustness with a fast turn-on speed. The proposed new ESD protection scheme, which is designed with only low-voltage devices, is an excellent and cost-efficient solution to protect mixed-voltage I/O interfaces. To greatly improve ESD robustness of the vacuum-fluorescent-display (VFD) driver IC for automotive electronics applications, a new electrostatic discharge protection structure of high-voltage P-type silicon controlled rectifier (HVPSCR) embedded into the high-voltage PMOS device is proposed. By only adding the additional N+ diffusion into the drain region of high-voltage PMOS, the TLP-measured secondary breakdown current (It2) of output driver has been greatly improved greater than 6A in a 0.5-µm high-voltage CMOS process. Such ESD-enhanced VFD driver IC, which can sustain HBM ESD stress of up to 8kV, has been in mass production for automotive applications in car without latchup problem. Moreover, with device widths of 500um, 600um, and 800um, the MM ESD levels of the HVPSCR are as high as 1100V, 1300V, and 1900V, respectively. The dependences of drift implant and layout parameters on ESD robustness in a 40-V CMOS process have been investigated in silicon chips. From the experimental results, the HV MOSFETs without drift implant in the drain region have better TLP-measured It2 and ESD robustness than those with drift implant in the drain region. Furthermore, the It2 and ESD level of HV MOSFETs can be increased as the layout spacing from the drain diffusion to polygate is increased. It was also demonstrated that a specific test structure of HV n-type silicon controlled rectifier (HVNSCR) embedded into HV NMOS without N-drift implant in the drain region has the excellent TLP-measured It2 and ESD robustness. Moreover, due to the different current distributions in HV NMOS and HVNSCR, the dependences of the TLP-measured It2 and HBM ESD levels on the spacing from the drain diffusion to polygate are different. In this thesis, the novel ESD protection circuits have been developed for mixed-voltage I/O interfaces and high-voltage CMOS process with high ESD robustness. Each of the ESD protection circuits has been successfully verified in the testchips. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT009111515 http://hdl.handle.net/11536/42780 |
显示于类别: | Thesis |
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