增進複晶矽薄膜電晶體特性之先進技術

Abstract

本論文分為兩個部分。第一個部分，將修正蕭特基阻障鰭狀電晶體（Modified-Schottky-Barrier FinFET, MSB FinFET）的概念延伸應用到修正蕭特基阻障薄膜電晶體(MSB TFT)。第二個部分則探討將二氧化鉿做為薄膜電晶體時，閘極區域之外的二氧化鉿的去除技術。 在經過離子植入矽化物及其後的活化製程後，可以形成超淺源極/汲極延伸(S/D extension)以調變蕭特基阻障性質。此超淺源極/汲極延伸可以降低傳統蕭特基接面漏電。此超淺源極/汲極延伸可連接通道以及源極/汲極金屬矽化物，使得修正蕭特基阻障薄膜電晶體可以維持較低的源極注入阻抗而得到較高的導通電流。在元件導通模式下，較高的導通電流是由矽化物直接穿隧超淺源極/汲極延伸所形成較薄的阻障而得到的穿隧電流，此較薄的阻障不同於傳統較寬的蕭特基阻障。在元件關閉模式下，超淺源極/汲極延伸所形成的較寬且較高的蕭特基障則阻擋了載子的穿隧。 在修正蕭特基薄膜阻障電晶體的製程上，單一金屬矽化物-矽化鎳可以同時適用於N型以及P型電晶體，一次500℃快速退火步驟即可形成良好的自動對準矽化鎳結構。對於修正蕭特基阻障特性，溫度是最重要的製程參數。超淺源極/汲極延伸可以在六百度的低溫下形成，而當溫度高過七百度，由於熱應力或表面能的不平衡將會導致結塊現象。因此五百度是一個合適的矽化溫度而六百度則可以形成超淺源極/汲極延伸。除此之外。高於5×1015 cm-2 的離子佈植濃度將可以在低溫環境下很容易的形成超淺且高濃度的源極/汲極延伸。 在本論文的第二部份中，由於二氧化鉿是目前較被看好的材料之一，欲完成元件製程整合，閘極蝕刻後的二氧化鉿去除是一個必須解決的課題。由於二氧化鉿在經過高溫沈積或高溫退火處理之後很難被濕蝕刻，因此本論文提供了兩階段蝕刻製程。前者可以藉由物理性的離子撞擊來破壞二氧化鉿結構並產生許多Hf-O鍵結以及不完美的Hf-O鍵結。後者則是藉由與這些鍵結的化學反應來移除薄膜。這樣一來，化學沈積的二氧化鉿薄膜將可以有效的被兩階段蝕刻製程所蝕刻。

This thesis consists of two parts. In the first part, the concept of Modified-Schottky-Barrier (MSB) FinFET was employed to fabricate MSB TFTs. In the second part, wet etching technique of HfO2 film was developed. It is a key process step to integrate HfO2 film into TFTs process. It is demonstrated that Ni-silicide can be applied to both n-channel and p-channel devices simultaneously. Process complexity can be reduced greatly. Although two-step silicidation is suggested for bulk CMOSFETs and MSB FinFETs, Ni-salicide structure can be formed by one step RTA at 500℃ in MSB TFTs because the Si source is limited in the S/D region and device dimension of TFTs is much larger than that of CMOSFETs or FinFETs. MSB TFTs with the suitable activation process shows the superior I-V characteristics compared to CN TFTs and SB TFTs. A rapid thermal activation at temperature between 600℃ to 650℃ results in the best device performance for both MSB pTFTs and MSB nTFTs. When MSB TFTs are activated at the temperature higher than 700℃, Ni-silicide agglomerates at gate electrode and device performance degrades. At suitable activation temperature, 30 seconds RTA is a suitable activation time for MSB TFTs. Besides these, higher implantation dose can provide more dopants to enhance device performance. Considering the device geometries, narrower channel width has few grain boundaries and trap states; therefore, threshold voltage slightly decreases. On the other hand, strong reverse short channel effect appears due to traps states of MMGB’s. Fortunately, it is not necessary to scale channel length of TFTs down to around 1um and hydrogen contained plasma treatment is expected to passivate defects at MMGB’s. It is strong believed that the MSB TFTs can achieve excellent device performance and can be applied to LTPS TFTs due to its low thermal budget feature. Temperature, including deposition temperature and post-deposition annealing temperature, is the most important factor to affect the wet etching behavior of HfO2 film. The film structure deposited at different temperatures is studied in this chapter and the influence of PDA temperature is also examined. The higher deposition temperature causes fewer dangling Hf-O bonds and higher post-deposition annealing temperature reconstructs the dangling and imperfect Hf-O bonds. Therefore, the wet rate is lower. Fortunately, implantation process can help to degrade Hf-O bonds, and let the HfO2 films become wet etch-able.