标题: 奈米点非挥发性记忆体元件之研究
Study on Nanocrystal Nonvolatile Memory Devices
作者: 林泩宏
Sheng Hung Lin
施 敏
张鼎张
Simon M. Sze
Ting-Chang Chang
电子研究所
关键字: 奈米点;Nanocrystal
公开日期: 2003
摘要: 传统的非挥发性记忆体是利用复晶矽浮停闸(floating gate)做为载子储存的单元,当浮停闸储存由通道注入的电子之后,元件的起始电压就会发生改变,利用起始电压的差异作为记忆体0和1逻辑的定义。然而,由于浮停闸是连续的一层半导体薄膜,在反覆的操作下,一旦穿隧氧化层(tunnel oxide)出现漏电路径,储存的电荷就会全部流失,记忆体就会失效,因此穿隧氧化层的厚度无法缩减下来,操作电压无法降低,速度也无法增快。一般认为当元件通道长度达到65 nm时,便是此种结构的极限。本研究利用半导体或金属奈米点作为电荷储存的单元,可以减少穿隧氧化层的厚度,而不损失可靠性,进而降低操作电压,并使元件缩小密度提高,操作速度增快。
利用半导体或金属奈米点作为电荷储存的单元。在元件的反覆操作下,即使穿隧氧化层产生缺陷或漏电路径,所损失掉的储存电子,仅是单一奈米点的电子漏失,对整体元件特性的影响并不明显。因此,穿隧氧化层的厚度得以缩减,使得操作速度提升,元件积集度增加,元件可操作的次数(endurance)以及保存时间(retention)也同时得到改善。当电子储存在奈米点时,由于库伦阻绝(Coulomb blockade)效应,储存的电子会限制后续电子的注入。奈米点的库伦阻绝效应使得记忆体元件的储存及操作更加的稳健。当闸极偏压使通道产生反转层后,通道的电子藉由直接穿隧效应或是F-N穿隧效应通过穿隧氧化层,而让奈米点捕获,是为写入动作。当闸极偏压反向时,储存的电子便经由穿隧氧化层回到通道,是为抹除动作。藉由电容-电压(C-V)量测,当电子注入奈米点之后,元件之起始电压会发生偏移,此偏移的量即定义为记忆体元件的记忆窗。
本研究提出于穿隧氧化层上利用低压化学气相沈积(LPCVD)成长SiGe薄膜,并以热氧化方式,使矽氧化成为二氧化矽作为控制氧化层,而锗元素向下析出在穿隧氧化层上,作为载子储存的单元。由穿透式电子显微镜图(TEM)知,锗奈米点析出于穿隧氧化层上,穿隧氧化层厚度约4.5奈米,锗奈米点的尺寸大约5.5奈米,经由电性计算密度大约为4.2*1011/cm2。由图中可估算,在5伏的操作电压下,记忆窗大约有0.42伏,足够作为记忆体定义0与1。然而当增加SiGe薄膜热氧化时间,锗便会氧化为氧化锗,形成氧化锗奈米点。经由电性量测后发现,氧化锗奈米点也确实有记忆体特性,另外经由x-ray absorption near edge spectroscopy (XANES)也证实穿透式电子显微镜照片中的奈米点成分为氧化锗,我们并且提出了一个物理模型来解释此元件之记忆体效应。另外,在金属奈米点方面,我们提出利用铂金属溅镀于穿隧氧化层上,不需经过热处理,自我组装成核,铂(Pt)奈米点的制作方式,藉由制程上的改进,可形成金属奈米点并得到金属奈米点的记忆体特性,并且在5伏的操作电压下,达到0.25伏的起始电压偏移(记忆窗) 。
In a conventional nonvolatile memory, charge is stored in a polysilicon floating gate (FG) surrounded by dielectrics. The scaling limitation stems from the requirement of very thin tunnel oxide layer. For FG, once the tunnel oxide develops a leaky path under repeated write/erase operation, all the stored charge will be lost. Therefore, the thickness of the tunnel oxide can not be scaled down to about 7 nm.
To alleviate the scaling limitation of the conventional FG device while preserving the fundamental operating principle of the memory, we have studied the distributed charge storage approach such as the nanocrystal nonvolatile memory. Each nanodot will typically store only a handful of electrons; collectively the charges stored in these dots control the channel conductivity of the memory device. Nanocrystal charge storage offers several advantages, the main one being the potential to use thinner tunnel oxide without sacrificing nonvolatility. This is a quite attractive proposition since reducing the tunnel oxide thickness is a key to lowering operating voltages and/or increasing operating speeds. The improved scalability results not only from the distributed nature of the charge storage, which makes the storage more robust and fault-tolerant, but also from the beneficial effects of Coulomb blockade. A local leaky path will not cause a fatal loss of information for the nanocrystal nonvolatile memory device. Also, the nanocrystal memory device can maintain good retention characteristics and lower the power consumption.
We have fabricated a nonvolatile memory device embedded with Ge nanocrystals by a thermal oxidation of Si0.8Ge0.2 combined with a rapid thermal annealing process. The tunnel oxide in the nonvolatile memory is 4.5 nm-thick and with 5.5-nm Ge nanocrystals reside on it. A low operating voltage, 5V, is implemented and a significant threshold-voltage shift, 0.42V, is observed. Also, we have demonstrated the novel distributed charge storage with GeO2 nano-dots. The mean size and aerial density of the dots are estimated to be about 5.5 nm and 4.3×1011 cm-2, respectively. The composition of the GeO2 dots is confirmed by the XANES measurements. In electrical analyses, a significant memory effect is observed with a threshold voltage shift of 0.45V under 5-V operation. Also, a physical model is proposed to explain the charge storage via the interfacial traps of GeO2 nano-dots.
We have also proposed a simple process to fabricate metal nanocrystal memory which is one of the candidates that have great potential of achieving fast write/erase and long retention time simultaneously. Once the self-assembled nanocrystals have controllable density and size distribution, the metal nanocrystals can be incorporated into a standard MOSFET structure to fabricate nonvolatile memory devices.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009111544
http://hdl.handle.net/11536/43068
显示于类别:Thesis


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