元件圖案相依的金屬誘化側向結晶之複晶矽薄膜電晶體的製作與特性研究

Abstract

在此論文中，我們首先提出一個以標準四道光罩，所製作之元件圖案相依的金屬誘化側向結晶之複晶矽薄膜電晶體。根據實驗結果顯示，由於載子遷移率的提昇以及較佳的閘極控制能力，電晶體的電特性被大幅的改善。研究中發現，載子遷移率是與元件的通道寬度相依。對同樣閘極長度為5 um的元件而言，遷移率隨著通道寬度的縮減而增加，這是由於窄通道效應提升了複晶矽晶粒的側向尺寸。此外，實驗結果也顯示出，對相同十條奈米通道的元件，隨著閘極長度的下降，載子的遷移率亦隨之提升。這是由於閘極所跨的通道內，存在較少的複晶矽晶粒邊界缺陷所造成的。此外在短通道元件的研究，藉由比較單一通道與十條奈米通道的元件，我們發現單一通道的元件展現出接觸碰穿的現象，然而十條奈米通道的元件，依然保持著良好的開關特性。此現象可被解釋為，十條奈米通道的元件，由於它的環繞式閘極的結構，使其有較佳的閘極控制能力來降低橫向電場，以抑制短通道的效應。此元件圖案相依的，金屬誘化側向結晶之複晶矽薄膜電晶體的製程，完全相容於目前互補式金氧半(CMOS)場效電晶體的技術，而且不需要額外的光罩製程。此元件可被運用於高效能的複晶矽薄膜電晶體積體電路，尤其是在主動式薄膜電晶體液晶顯示器(AMLCD) ，以及三維立體的金氧半場效電晶體積體電路。

In this thesis, we firstly develop a new pattern-depended MILC thin film transistors (PDM TFTs) with standard four masks process. The experiment results demonstrate that the electrical properties of PDM TFT’s can be significantly improvement by carrier mobility enhancement and superior gate controllability. Experiment results show that the field effect mobility is highly depended on multi-channel width. For the same gate length L=5um, the field effect mobility increasing with channel number, resulting its polysilicon grain size enhanced by channel width limitation effect. In addition, experiment results also show that at the same ten multiple nano-wire channels, the field effect mobility increasing with gate length decreasing from L = 10 um, L = 5 um, L = 2 um to L = 1 um, resulting its polysilicon grain boundary defects lowering. Moreover, in short channel effect (L = 1um) study, comparing the single channel and ten multiple nano-wire channels devices. The single channel TFT shows punch-through phenomena. It ca be explain that the ten multiple nano-wire channels TFT has the better gate controllability due to its nano-wires structure behavior than single channel TFT. The lateral electrical field of ten multiple nano-wire channels TFT can be effectively reduced by additional two side-gates control. These PDM TFTs process is compatible with CMOS technology, and involves no any extra mask process. Such PDM TFTs are thus highly promising for use in future high-performance polysilicon TFT applications, especially in AMLCD and 3D MOSFET stacked circuits.