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dc.contributor.author高志承en_US
dc.contributor.authorKao, Chih-Chengen_US
dc.contributor.author李毅郎en_US
dc.contributor.authorLi, Yih-Langen_US
dc.date.accessioned2014-12-12T01:33:50Z-
dc.date.available2014-12-12T01:33:50Z-
dc.date.issued2009en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT079655504en_US
dc.identifier.urihttp://hdl.handle.net/11536/43306-
dc.description.abstract近幾年來,結構化特定應用積體電路的設計方式在特殊應用積體電路以及現場可程式化邏輯閘陣列這兩種設計方式中逐漸佔有一席之地,此種新的設計方法能平衡特殊應用積體電路以及現場可程式化邏輯閘陣列這兩種設計方式的差距。為了要攤銷更多的光罩成本,結構化特定應用積體電路的時脈配置是內建的,但是這種時脈架構會增加配置器的負擔,因為它需要考量每個區域所使用的時脈數量之限制。這個作品提出一個演算法來處理結構化特定應用積體電路的配置問題,我們的方法可利用現有的標準元件配置器來產生一個初始的配置結果,然後再針對這個初始結果,利用群聚的方法完成合法化並同時滿足型別配對以及時脈限制。我們所提出的群聚法和預先指定時脈演算法在群聚節點或指定時脈時,可考慮節點的位移值和連線分佈來完成合法化。在完成合法後,我們利用所提出的區塊層級線長改進演算法來進一步改進線長。實驗結果顯示出我們的配置器在使用mPL6和Capo這兩個標準元件配置器下,比RegPlace配置器的半周長分別改進了6.0百分比和8.0百分比。另外,在我們提出的演算法下,任何標準元件配置器只需要花少許的CPU 時間即可處理結構化特定應用積體電路的配置問題。zh_TW
dc.description.abstractStructure ASIC has emerged to fill the gap between ASIC and FPGA in recent years. To share more mask for amortizing the mask cost, the clock scheme is intrinsic and it makes placement stage more complicated by considering clock constraint. This work presents an algorithm to handle the placement problem of structure ASIC. First, our approach utilizes any existing standard-cell placer to generate an initial placement solution, and then we legalize this initial solution with simultaneously satisfying site type matching and clock constraint. The proposed clustering technique and clock pre-assignment algorithm consider node displacement and netlist distribution in clustering cells or assigning clock to complete legalization. After that, we apply an iterative block level wirelength improvement technique to further improve wirelenth. Experimental results indicate that our placer achieves 6% and 8% better wirelength than RegPlace [17] on average with mPL6 and Capo respectively; and incorporating with our algorithm, any existing standard-cell placer can complete structure ASIC placement with only small expense of CPU time.en_US
dc.language.isoen_USen_US
dc.subject結構化特定應用積體電路zh_TW
dc.subject配置器zh_TW
dc.subject群聚法zh_TW
dc.subjectStructure ASICen_US
dc.subjectplaceren_US
dc.subjectClusteringen_US
dc.titleKDL: 應用群聚法考慮時脈限制的結構化特定應用積體電路配置器zh_TW
dc.titleKDL: Clustering-Based Structure ASIC Placer Considering Clock-Domain Constrainten_US
dc.typeThesisen_US
dc.contributor.department資訊科學與工程研究所zh_TW
Appears in Collections:Thesis