在即時編譯器中針對混合固定長度指令集所設計的暫存器分配演算法以求縮減程式碼

Abstract

在嵌入式系統中儲存程式的記憶體是相當重要的資源，於是減少程式碼的大小成為了重要的議題。其中一種解決方法是用“混合寬度指令集架構”。一般而言，這樣的架構提供了兩種固定長度指令集，能夠執行一般指令(通常為32位元)以及短指令(通常為16位元)。在這樣的架構中程式可由兩種指令組合而成，如果程式使用了越多的短指令其程式碼大小就越小。然而短指令上有著一些限制，例如只能使用較短立即值範圍以及存取較少的暫存器，這些都影響了程式中短指令使用的比例多寡，其中如何分配可被短指令存取的暫存器影響最大。這篇論文中我們針對混合寬度指令集架構提出了一個適用於即時編譯器的快速暫存器演算法，這個演算法能得到26%程式碼縮減。

In embedded system, memory is a precious resource, and that reducing program code size becomes an important issue. One promising approach for code reduction is employing “mixed-width instruction set architecture (ISA)”. This kind of architecture usually provides two fixed width instruction sets, a long instruction set (usually 32-bit) and a short instruction set (usually 16-bit). In other words, program can be compiled into native code by using these two kinds of instructions mixedly. Obviously, the more short instructions are used in the program, the smaller program will be. However, there are some limitations for using short instructions. For example, they can only encode smaller range of immediate value and a subset of whole architecture registers. The short of registers is the most important issue among all limitations. Consequently, a register allocation which can allocate register more appropriately is needed for mixed-width ISA. In this thesis we propose a fast specific register allocation algorithm for JIT compiler which is more suitable for mixed-width instruction set architecture than traditional ones and get about 26% code size reduction with neglectable performance loss.