標題: | 多輸入多輸出鎖相迴路軟體化之研究 The Study of MIMO Software-defined Phase-locked Loop |
作者: | 黃則斌 Huang, Ze-Bin 許騰尹 Hsu, Terng-Yin 資訊科學與工程研究所 |
關鍵字: | 鎖相迴路;軟體鎖相迴路;PLL;Software-define PLL;SDPLL |
公開日期: | 2008 |
摘要: | 本篇論文提出了可軟體控制及開發的多輸入多輸出軟體鎖相迴路平台(MIMO-SDPLL)。此平台並結合了數個矽智財包括CPU及鎖相迴路的相關模組。CPU的引進,為平台提供有彈性的軟體控制及運算。在輸出規格需要大幅更動時,以變更軟體的方式即能符合所需要的規格。本論文所提出的軟體鎖定演算法能達到高解析度鎖定的狀態並且以軟體的方式進行開發。多重時脈輸入能用軟體排程的方式進行處理。硬體方面,以2對2的架構進行作。所有的矽智財實作於UMC 90nm的製程上。 A software controllable and programmable MIMO software-defined phase-locked loop (MIMO-SDPLL) platform is presented in this paper. This platform combine several silicon IPs including CPU and PLL modules. CPU is introduced to provide flexible software controllability and computing power. When the specification needs substantially modify, replace the software at platform can fit the new specification. The proposed software tracking algorithm can reach high-resolution phase-locked and development by software. Multi-clock can be handled with software scheduling. In hardware, 2x2 MIMO-SDPLL architecture is implemented in this work. All IP cores implement at UMC 90nm process. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT079655588 http://hdl.handle.net/11536/43394 |
Appears in Collections: | Thesis |
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