新穎低溫多晶矽薄膜電晶體之製程與□定度分析

Abstract

在本篇論文,一個含有較厚的源/汲極區和較薄的通道的新穎複晶矽薄膜電晶體被提出而加以研究．在提出的結構中，和傳統的堆疊式薄膜電晶體比較下，我們只需較少的４道光罩製程．提出的結構中，它有不錯的開╱關電流比仍維持在良好的擺幅（約1.51）．在開╱關電流比上，在閘極電壓為5V下,仍維持在1.85x107 左右．而更進一步地看，在閘極電壓加至30V時，提出的薄膜電晶體仍展現了一個較佳的飽和電流特性．同時在漏電流方面，也比傳統的降低了2.96倍．

In this paper, a novel structure of the polycrystalline silicon thin-film transistors (Poly-Si TFT’s) with a thicker source/drain and a thin channel have been developed and investigated. In the proposed structure, the thick source/drain and a thin active region could be achieved with only four mask steps, which are less than conventional stagger TFT. The proposed TFT has and higher Swing (~1.51). The on/off ratio is 1.85x107 for Vgs= 5 V Moreover, the proposed TFT exhibits excellent current saturation characteristics at high bias (Vgs= 30 V) and has more than 2.96 times reduction in minimum off-state current compared to conventional TFT’s.

Index Terms—stagger source/drain, On/Off current ratio, poly-Si TFT.