Full metadata record
DC FieldValueLanguage
dc.contributor.author翁世學en_US
dc.contributor.authorShih-Hsueh Wengen_US
dc.contributor.author張國明en_US
dc.contributor.author桂正楣en_US
dc.contributor.authorKow-Ming Changen_US
dc.contributor.authorCheng-May Kweien_US
dc.date.accessioned2014-12-12T01:34:15Z-
dc.date.available2014-12-12T01:34:15Z-
dc.date.issued2004en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT009111577en_US
dc.identifier.urihttp://hdl.handle.net/11536/43423-
dc.description.abstract在本篇論文,一個含有較厚的源/汲極區和較薄的通道的新穎複晶矽薄膜電晶體被提出而加以研究.在提出的結構中,和傳統的堆疊式薄膜電晶體比較下,我們只需較少的4道光罩製程.提出的結構中,它有不錯的開╱關電流比仍維持在良好的擺幅(約1.51).在開╱關電流比上,在閘極電壓為5V下,仍維持在1.85x107 左右.而更進一步地看,在閘極電壓加至30V時,提出的薄膜電晶體仍展現了一個較佳的飽和電流特性.同時在漏電流方面,也比傳統的降低了2.96倍.zh_TW
dc.description.abstractIn this paper, a novel structure of the polycrystalline silicon thin-film transistors (Poly-Si TFT’s) with a thicker source/drain and a thin channel have been developed and investigated. In the proposed structure, the thick source/drain and a thin active region could be achieved with only four mask steps, which are less than conventional stagger TFT. The proposed TFT has and higher Swing (~1.51). The on/off ratio is 1.85x107 for Vgs= 5 V Moreover, the proposed TFT exhibits excellent current saturation characteristics at high bias (Vgs= 30 V) and has more than 2.96 times reduction in minimum off-state current compared to conventional TFT’s. Index Terms—stagger source/drain, On/Off current ratio, poly-Si TFT.en_US
dc.language.isoen_USen_US
dc.subject薄膜電晶體zh_TW
dc.subject堆疊zh_TW
dc.subjectpoly-Si TFTen_US
dc.subjectLTPSen_US
dc.subjectstagger source/drainen_US
dc.subjectOn/Off current ratioen_US
dc.title新穎低溫多晶矽薄膜電晶體之製程與□定度分析zh_TW
dc.titleThe Fabrication and Stability Study of the Novel Structure of LTPS TFTsen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
Appears in Collections:Thesis


Files in This Item:

  1. 157701.pdf

If it is a zip file, please download the file and unzip it, then open index.html in a browser to view the full text content.