以記憶體為基礎的多標準前端錯誤更正

Abstract

前端錯誤更正在通訊系統是一個相當重要的功能，它主要包含攪拌器(scrambler)、 里德所羅門編碼(Reed-Solomon coding)、交錯器(interleaver)和迴旋編碼(trellis coding)。 對於效能和複雜度的考量，隨著不同的應用而會有不同的設計參數。本論文提出一個高效率節省功率和面積架構的多標準前端錯誤更正解碼器以符合不同系統的要求，而所提出的多標準前端錯誤解碼器可以完全相容於ITU-T J.83的纜線數據系統並且可相容於數位視訊廣播和ATSC數位電視等系統。我們所提出的多標準前端錯誤更正解碼器主要包含一以記憶體來儲存及更正資料的多模里德所羅門解碼器和一以記憶體為基礎及位址產生器的泛用型卷積解交錯器(convolutional de-interleaver)，皆具有以最小晶片面積達到最多功能的特色。以0.18微米 1P6M CMOS 製程實作的結果大約需要5萬4千個邏輯閘以及6千位元的嵌入式靜態隨機存取記憶體，最快可以達到83MHz(600Mbps)的工作頻率。平均消耗功率在最複雜的解碼模式及在83MHz之工作頻率下大約是45mW；在滿足系統規範之操作參數環境下，平均消耗功率大約5.4mW。

Forward Error Correction (FEC) which mostly contains scrambler, Reed-Solomon coding, interleaving, and trellis coding is a key component in communication system. For the performance and complexity issues, design parameters are different in various applications. In this thesis, a multi-standard FEC decoder is presented to meet different system requirements with a power and area efficient architecture. The proposed multi-standard FEC decoder is fully compliant to ITU-T J.83 cable modem system and is also compatible to DVB-T and ATSC Digital TV, etc. The proposed multi-standard FEC decoder, including a multi-mode Reed-Solomon decoder with memories to store and correct the received data and a memory-based universal convolutional interleaver with a simple address generator, has the advantage of lowest overhead. With 0.18mm 1P6M CMOS technology, the implemented chip shows the FEC decoder can work at 83MHz (600Mbps) while costs 54.5K gate counts and two 376x8 bits embedded duel-port SRAM. The average power consumption in full spec. mode is about 45mW at 83Mhz. While running at 7MHz that meets symbol rate of cable modem, the power dissipation is 5.4mW.