應用於六百億赫茲通訊系統的毫米波互補式金氧半電路分析與設計

Abstract

本篇論文主要闡述了適用於60GHz低功率通訊系統的毫米波互補式金氧半電路其設計方法及製作技術。論文中包含下列三個部分：(1)次諧波注入鎖住式三倍頻器的分析、模型建立與設計方法；(2)整合注入鎖住式頻率倍乘器的60GHz鎖相迴路電路分析及設計；(3)整合注入鎖住式三倍頻器的60GHz直接降頻接收機的設計。 首先，本論文提出以及分析一個具有差動輸出的互補式金氧半次諧波注入鎖住式三倍頻器，並且設計使其適用於K頻段和V頻段。根據所提出的次諧波注入鎖住式三倍頻器的架構，發展出鎖頻範圍及輸出相位雜訊的模型。K頻段的注入鎖住式三倍頻器採用了0.18微米互補式金氧半製程設計與製作。由量測結果可知：當功率消耗為0.45毫瓦特和輸入功率為4dBm時，鎖頻範圍為1092MHz；輸出的三階諧波對於一階、二階、四階及五階的諧波抑制比分別為22.65、30.58、29.29及40.35分貝；當使用可變電容及增加功率消耗到2.95毫瓦特時，K頻段的注入鎖住式三倍頻器鎖頻範圍可達到3915MHz。另外設計了採用0.13微米互補式金氧半製程的V頻段的注入鎖住式三倍頻器。量測結果顯示：當功率消耗為1.86毫瓦特和輸入功率為6dBm時，鎖頻範圍為1422MHz。可以發現到此次所提出的注入鎖住式三倍頻器，其鎖頻範圍與傳統利用可變電容來調整輸出頻率的壓控振盪器是相似的。 其次，本論文提出了一個能夠產生60GHz輸出的整合注入鎖住式頻率倍乘器之鎖相迴路。此60GHz鎖相迴路整合了壓控振盪器、注入鎖住式頻率倍乘器、除32的頻率除法器、相位頻率偵測器、電荷幫浦和迴路濾波器。因為所提出的注入鎖住式頻率倍乘器能夠產生壓控振盪器的五階諧波訊號，所以壓控振盪器僅需工作在所需要頻率的五分之一。此鎖相迴路採用了0.18微米互補式金氧半製程設計與製造。由量測結果可得：鎖相迴路輸出頻率為53.04到58.0GHz及輸出功率為–37.85dBm，相位雜訊在1MHz及10MHz偏移量下每赫茲分別較主訊號低85.2及90.9分貝，參考突波訊號較主訊號低65分貝。在1.8伏特的電壓工作下，其電路功率消耗為35.7毫瓦特。整個鎖相迴路的晶片面積為0.96×0.84平方毫米。 最後，本論文提出一個應用於60-GHz頻段且整合次諧波注入鎖住式三倍頻器的直接降頻接收機。本論文提出的直接降頻接收機包含了低雜訊放大器、四相位降頻混頻器、一個20-GHz的四相位壓控振盪器、兩個次諧波注入鎖住式三倍頻器、兩個中頻放大器以及兩個輸出緩衝級。在這個接收機中，本地振盪器的訊號是經由一個操作在三分之一載波的四相位壓控振盪器串接兩個次諧波注入鎖住式三倍頻器來提供。由於四相位壓控振盪器的頻率偏移，所以產生的本地振盪器訊號最高頻率只有55.03GHz。在以射頻訊號55.03GHz以及中頻訊號100MHz時的量測結果可知：接收機的增益為18.2分貝、雜訊指數16.96分貝、增益1分貝壓縮點在輸入端為–17.0dBm、三階互調失真點為–7.6dBm。本論文提出的接收機是使用0.13微米的互補式金氧半製程所製作。在供應電壓1.2伏特時的總功率消耗為31.0毫瓦特，整個直接降頻接收機的晶片面積為1.21×1.03平方毫米。 經由模擬以及量測結果可以證實，本論文所提出的注入鎖住式三倍頻器可適用於低功率高性能工作在毫米波頻段的收發機。在未來中，更進階的研究將可以整合低功率的單一晶片收發機以及頻率合成器。

In this thesis, the design methodologies and implementations of millimeter-wave CMOS circuit for 60-GHz low-power communication system are presented. There are three parts: (1) the analysis, modeling, and design of the subharmonic injection-locked frequency tripler (ILFT); (2) the analysis and design of 60-GHz phase-locked loop (PLL) integrated with injection-locked frequency multiplier (ILFM); and (3) the design of 60-GHz direct-conversion receiver integrated with ILFT. At first, K-band and V-band CMOS differential subharmonic ILFTs are proposed, analyzed, and designed. Based on the proposed ILFT structure, models for the locking range and the output phase noise are developed. A K-band ILFT is designed and fabricated using 0.18-μm CMOS technology. The measured locking range is 1092 MHz with a dc power consumption of 0.45 mW and an input power of 4 dBm. The harmonic rejection-ratios are 22.65, 30.58, 29.29, 40.35 dBc for the first, second, fourth, and fifth harmonics, respectively. The total locking range of the K-band ILFT can achieve 3915 MHz when the varactors are used and the dc power consumption is increased to 2.95 mW. A V-band ILFT is also designed and fabricated using 0.13-μm CMOS technology. The measured locking range is 1422 MHz with 1.86-mW dc power consumption and 6-dBm input power. It can be seen that the locking range of the proposed ILFT is similar to the tuning range of a conventional varactor-tuned bulk-CMOS voltage-controlled oscillator (VCO). Secondly, a novel CMOS PLL integrated with ILFM that generates the 60-GHz output signal is proposed. The proposed 60-GHz PLL is composed of VCO, ILFM, 1/32 frequency divider, phase/frequency detector, charge pump, and loop filter. Because the proposed ILFM can generate the fifth-order harmonic frequency of VCO output, the operational frequency of the VCO can be reduced to only one-fifth of the desired frequency. The PLL is designed and fabricated in 0.18-μm CMOS technology. The output frequency range of the proposed PLL is from 53.04 GHz to 58.0 GHz with output power of –37.85 dBm. The measured phase noises at 1 MHz and 10 MHz offset from the carrier are –85.2 and –90.9 dBc/Hz, respectively. The reference spur level of –40.16 dBc is measured. The dc power dissipation of the fabricated PLL is 35.7 mW under a 1.8-V supply. The chip area including pads is 0.96 mm × 0.84 mm. Finally, a 60-GHz direct-conversion receiver integrated with ILFT is proposed. The proposed direct-conversion receiver front-end is composed of a low-noise amplifier (LNA), I/Q quadrature down-conversion mixers, a 20-GHz QVCO, two ILFTs, two IF amplifiers, and two output buffers. In the proposed receiver, the local oscillator (LO) signals are generated by QVCO operated at only one-third of carrier frequency cascade with the two ILFTs. Due to the frequency shift of QVCO, the maximum RF frequency is only 55.03 GHz. The measured results show a receiver gain of 18.2 dB, a noise figure of 16.96 dB with RF frequency of 55.03 GHz and IF frequency of 100 MHz, channel bandwidth of 2 GHz with LO frequency of 55.02 GHz, an input-referred 1-dB compression point (P1dB) of –17.0 dBm, and input third-order inter-modulation intercept point (IIP3) of –7.6 dBm. The proposed receiver is implemented using 0.13-μm CMOS technology and draws 25.84 mA from a 1.2-V supply. The total chip area, including testing pads, is only 1.21 mm × 1.03 mm. It is believed that the proposed ILFT can be used in low-power high-performance transceiver design in the millimeter-wave band. Further research for low-power single chip transceiver and frequency synthesizer can be integrated in the future.