適用於正交分頻多工系統之快速傅立葉轉換處理器設計

Abstract

為了設計一個具低複雜度、低成本的可變長度快速傅立葉轉換處理器以適用於多種正交分頻多工的通訊系統，本論文由演算法至架構層次研究各種關於快速傅立葉轉換的技術。本論文並提出了改進的可變長度資料位址產生器、新的轉動因子產生器以及應用新座標旋轉演算法的新快速傅立葉轉換處理單元。其中可變長度資料位址產生器將原先耗費面積的桶形移位器設計簡化成應用多工器的簡單定址函數設計；相較於現行的快速傅立葉轉換運算之轉動因子產生器，新的轉動因子產生器擁有高速與低複雜度的優點；相較於已知的座標旋轉設計，新的座標旋轉演算法與其快速傅立葉轉換處理單元設計擁有較少的重複執行次數，而且應用座標旋轉演算法的快速傅立葉轉換處理單元不需要額外的記憶體來儲存轉動因子。最後，本論文提出一個以座標旋轉演算法來設計處理單元之可變長度快速傅立業轉換處理器的架構，並可適用於802.16a、數位音訊廣播、以及數位影像廣播等多種通信標準。

In order to design a low-complexity and low-cost variable-length FFT processor module suitable for various OFDM communication systems, the thesis first studies various design techniques from algorithm level to architecture level. Then the thesis proposes an improved variable-length data address generator, a new twiddle factor generator and a new CORDIC-based FFT PE based on a new CORDIC algorithm. The variable-length data address generator simplifies the original area-consuming barrel-shifter based designs with a few simpler multiplexer-based addressing functions. The twiddle factor generator has the merit of low complexity and high speed over the existing twiddle factor generators for practical FFT operations. A CORDIC-based FFT PE has the advantage that it does not need extra memory to store twiddle factors. The new CORDIC algorithm and its FFT PE design have lower iteration counts than the known CORDIC design. Finally, the thesis synthesizes a multi-standard variable-length CORDIC-based FFT processor, which is suited for 802.16a, DAB and DVB-T.