鈦金屬在TSV直通矽晶穿孔中的金屬薄膜覆蓋率研究

Abstract

TSV直通矽晶穿孔(Through-Silicon Via)封裝製程是3D-IC封裝的主要技術，其中在通孔(Via)中以金屬濺鍍(PVD)的方式濺鍍金屬介電以及種子金屬薄膜層為主要的製程步驟之一。由於TSV通孔的特殊幾何構型將造成金屬濺鍍薄膜在通孔側壁以及底部的不均勻成膜，並影響後續電鍍製程的進行，且可能破壞後續製程電性的可靠度。在本報告當中，我們試著在不增加任何額外的硬體設備的情況之下，以標準化的金屬濺鍍腔體，進行各項製程參數的調變，觀察對濺鍍鈦金屬薄膜所造成之影響，並探討其可能之原因；以及觀察鈦金屬的濺鍍薄膜在小深寬比的通孔(AR 1.5)以及大深寬比的通孔(AR 5.0)當中所能達到的最佳通孔底部金屬覆蓋率。

TSV (Through-Silicon Via) is the key technology of 3D-IC package. To sputter thin and continuous barrier/seed metal layers inside via is essential process flow of TSV procedure. Due to “Bosch Procedure” in Silicon-Etching process produces unusual “scallop” side wall profile of vias, this makes even more difficult to get evenly coating of sputtered metal film on side wall and bottom of via. This may suffer the following EP procedure (Electronic Plating) and over-all production yield lost. Within this report, we try to monitor couple process parameters (DC power, RF bias power, and Process pressure) in standard PVD chamber, which does not have any extended hardware module to help via filling. We observe how those process parameters influence step coverage performance in via bottom to describe the best bottom step coverage performance we can get in both small (AR 1.5) and higher Aspect-Ratio (AR 5.0) vias.