一個使用和差調變器的2.4GHz直接調變發射器

Abstract

由於近年來，無線通訊產品的應用越來越普及，所以有許多新的系統因應此潮流而產生，而這些新的射頻系統無不朝向高整合度、低成本、低功效這幾方面發展且要同時滿足高效能這個大前題，也因此這篇論文將會針對這些目標， 並著重於無線通訊的發射器部分，並滿足1Mb/s 的資料傳輸速率。 我們利用一個數位補償的方法，可使得傳輸資料量可以大於非整數型的頻率合成器的頻寬，而使用這種方法，所製作的2.4GHz發射器，只需有非整數型的頻率合成器，和一個數位傳輸濾波器，即可完成每秒一百萬位元的資料傳輸率，而最主要實作在晶片中的是一個非整數型的頻率合成器，此頻率合成器主要包括有相位和頻率檢測器、電荷幫浦、電壓控制電壓振盪器、多係數除頻器和一個全數位化的Σ-Δ調變器。 此論文完成了一個使用和差調變器的2.4GHz直接調變發射器，使用台積電0.18μm 1P6M的互補式金氧半製程，此電路總消耗功率為16mW，供應電壓為1.8伏特，總晶片面積為1300μm×1300μm.。對電壓控制電壓振盪器的量測可知，其相位雜訊為-117.14dBc@1MHz 和 -120dBc@2MHz ，此量測結果符合藍芽系統的規範。

The use of wireless products has been rapidly increasing in the past few years, and there has been worldwide development of new systems to meet the needs of this growing market. As a result, new radio architectures and circuit techniques are being actively sought that achieve high levels of integration and low power operation while still meeting the stringent performance requirements of today’s radio systems. In this thesis, a DS fractional-N frequency synthesizer is proposed. Incorporating with base band digital modulation, a direct modulation transmitter architecture can be achieved for low cost and high performance design goals. This motivates the research of this work. The fractional-N frequency synthesizer is comprised of a DS modulator, a phase frequency detector, a charge pump loop filter, a LC voltage controlled oscillator , and a programmable frequency divider. Single loop, a 2bit and 3rd order modulator architecture is utilized for noise shaping. Moreover, a novel current matched charge pump circuit is proposed to reduce reference spurs. Finally, adaptive biasing VCO circuit is proposed for low noise performance. The single chip DS frequency synthesizer has been implemented in 0.18μm CMOS technology. The chip size is 1300μm´1300μm.The measured VCO phase noise is -117dBc/Hz@1MHz offset, and is -120dBc/Hz @ 2MHz offset .Operating under a 1.8v supply, total power dissipation is 16mW.