應用於三維堆疊互補式金氧半元件之單一晶界的複晶矽薄膜電晶體之研究

Abstract

近年來，由於元件微縮在製程方面遭遇許多瓶頸，使得積體電路密度提升之腳步漸趨緩慢，也意謂著以元件微縮提升積體電路密度已不再是有效率之作法。為加速提升積體電路之密度以達到摩爾定律所預期之腳步，三維積體電路(Three-Dimensional IC, 3D-IC)已被認為是最具有潛力之未來技術。相較於晶圓黏合(Wafer Bonding)製程僅能實現有限的堆疊密度與大量的晶圓消耗，在單一晶圓上進行逐層製程(Layer-by-Layer)的方式已被視為極可能實現最緊密堆疊之三維積體電路的作法。在逐層製程中，晶圓製程溫度必須保持夠低以避免較底層的元件性能遭受影響。因此，低溫複晶矽薄膜電晶體技術被認為極適合用於逐層製程以實現三維積體電路的夢想。在本篇論文中，我們提出被稱為梯台式通道結晶法(Elevated Channel Method)的方式來控制準分子雷射結晶之晶粒成長方向與晶界位置，以避免一般準分子雷射結晶常出現的缺點，如隨機的晶界分佈、較窄的製程窗口等等。我們也透過使用底閘極之梯台式通道結晶法製作出同時具有高性能且結構緊密的三維堆疊單一晶界通道之複晶矽薄膜電晶體，並嘗試此元件在互補式金氧半導體(CMOS)方面的應用。 在第一個部分中，我們研究使用底閘極結構製作出的單一晶界多晶矽薄膜並進一步探討其機制。由於底閘極結構之兩側角落提供了較厚的非晶矽層，進而在準分子雷射退火時得以扮演晶種的角色。當雷射能量密度控制到能使較薄的元件通道區域全熔，且接近底閘極角落較厚的區域半熔，然後由通道兩邊側向成長的晶粒沿著相對的方向往通道中間成長，進而在通道的中心只形成單一晶界，因此獲得大型的晶粒以提升元件的效能。藉由掃描式電子顯微鏡的分析，我們觀察到最大約0.7μm長的人為控制晶粒。除此之外，我們還發現對於上下兩層以立體堆疊並以不同厚度之間隔氧化層作區分之梯台式矽通道層而言，兩者的梯台式通道結晶法之製程窗口與最大晶粒尺寸幾乎相同。 在第二個部分中，我們研究了三維堆疊單一晶界通道之複晶矽薄膜電晶體的電性。就各個單一元件層內的元件來觀察，在沒有任何氫化處理與雜質活化的情形下，其N型元件之等效載子移動率超過300cm2/V-s，而P型元件則超過140 cm2/V-s。我們亦觀察到元件的均勻性被顯著提升，在量測二十個N型元件下，載子移動率之標準差小於12cm2/V-s，次臨界擺幅之標準差小於0.1V/decade，臨界電壓之標準差小於0.3V，而在量測二十個P型元件下，載子移動率之標準差小於5cm2/V-s，次臨界擺幅之標準差小於0.2V/decade，臨界電壓之標準差小於0.6V。在CMOS應用方面，將三維堆疊單晶界通道之複晶矽薄膜電晶體作為一個CMOS反相器(Inverter)使用時，不論供應電壓為高或低，我們都能得到相當明確的電位轉換特性。除此之外，當我們將P型元件製作於底層、並將間隔氧化層製作成與元件閘極氧化層同樣厚度時，在CMOS共通閘極趨動下，可讓底層P型元件受到位於其上方與下方兩個共通閘極同時趨動之雙閘極效應，進而增強底層P型元件之電性。藉由這樣的結構安排，將可使三維堆疊單一晶界通道複晶矽薄膜電晶體內的P型元件與N型元件之電性更為對稱，進而提升該元件於三維堆疊式CMOS應用上的實用性。 綜合以上所述，基於三維堆疊單晶界通道複晶矽薄膜電晶體技術具有製程簡單、低熱預算、高性能與絕佳均勻性等特點，該技術在未來三維積體電路之應用上勢必具有極大之潛力。

In recent years, the pace of improving packing density of integrated circuits (ICs) has become slower since the device scaling has met many bottlenecks in fabrication processes, which mean that the device scaling is not an efficient approach to higher IC packing density anymore. To speed up the pace of improving IC packing density to reach the prediction of Moore’s Law, three-dimensional integrated circuits (3D-ICs) have been thought as the most promising approach. Fabricating 3D-ICs with the layer-by-layer process on a single wafer has been seen as a very promising approach to the ultimate compact 3D-ICs, as opposed to the wafer bonding process which could result in finite packing density and high wafer cost. In the layer-by-layer approach, the wafer temperature during fabrication processes should be kept low enough not to affect the performance of devices in the lower layers. As a result, the low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) technology is thought to be suitable for the layer-by-layer process to realize the dream of 3D-ICs. In this thesis, we introduced the so-called elevated channel method to control the grain growth and the location of grain boundary, which could avoid many drawbacks of the conventional excimer laser crystallization, such as random grain boundaries, narrow process window, etc. With the aid of this method, the 3D-stacked single grain boundary (3D-SSGB) TFTs with high performance and compact structure had been fabricated for the 3D-stacked CMOS applications. In the first part, SGB polycrystalline silicon thin films fabricated by excimer laser annealing were investigated. The mechanisms of the elevated channel thin films were studied. A thick amorphous silicon region was formed in the both sides which served as the seeds for the lateral grain growth during excimer laser irradiation. As the laser energy density was controlled to completely melt the thin region in the channel and partially melt the thick region near the corner, the lateral grain growth starting from the sides of elevated channel could progress along the direction toward the center of channel region. There was only one longitudinal grain boundary in the center of the channel. Thus, a large-grain polycrystalline silicon thin film which would lead to improve the device performance was obtained. Large longitudinal grains artificially grown were observed to be about 0.7μm. Furthermore, the process window and the largest lateral grain size obtained by elevated channel method were almost the same for both the top and bottom elevated channel with different thicknesses of the separation oxide layer. In the second part, electrical characteristics of 3D-SSGB-TFTs were also studied. For the SGB-TFTs in individual layers of 3D-SSGB-TFTs, high performance SGB-TFTs with equivalent field-effect mobility exceeding 300 cm2/V-s for n-channel devices and 140 cm2/V-s for p-channel devices have been fabricated without any hydrogenation treatment and dopant activation. The uniformity was also improved by the elevated channel method. If twenty N-type / P-type SGB-TFTs were taken into discussion, the standard deviation of equivalent field-effect mobility, subthreshold swing, and threshold voltage was smaller than 12 / 5 cm2/V-s, 0.1 / 0.2 V/decade, and 0.3 / 0.6 V, respectively. For the CMOS applications, 3D-SSGB-TFTs as a CMOS inverter showed good voltage transfer characteristics at both high and low supply voltage. Moreover, by fabricating the P-type devices in the bottom device layer of 3D-SSGB-TFTs and the separation oxide layer as thick as the gate oxide layer, the performance of bottom P-type device would be enhanced during the CMOS operation due to the double-gate effect resulted from the common-gate driving. With these proper structure arrangements, more symmetric electrical characteristics of P-type and N-type devices of the 3D-SSGB-TFTs could be successfully achieved, and thus the practicality of 3D-SSGB-TFTs as a 3D-stacked CMOS would be well improved. To sum up, with the features such as simple process, low thermal budget, high device performance, and excellent device uniformity, the 3D-SSGB-TFT technology shows great potential in the 3D-IC applications.