高效能高頻功率放大器使用控制電路調整基極電壓之研究

Abstract

本論文探討如何設計高效率的CMOS射頻功率放大器。我們將討論如何使用控制電路調整基極電壓來提升低輸入功率時的PAE。此差動功率放大器是使用TSMC 0.18um CMOS製程並經由ADS momentum做EM模擬分析。在此設計一個操作5.3GHz的功率放大器， 並有最大輸出功率為27.9dBm，最大線性功率為26dBm，最大輸出PAE為34.3%，退後最大輸入功率12dB的PAE為12.2%的模擬結果。

Design of high Efficiency CMOS RF Power Amplifier will be investigated in this thesis. We will discuss how to use the adaptive body bias control circuit to enhance the PAE when the low input power is implemented. The differential power amplifier is implemented using TSMC 0.18um CMOS process The EM simulation results with ADS momentum. A design 5.3GHz power amplifier have the post simulation results Pout, sat is 27.9dBm, P1dB is 26dBm and the transducer gain is19.3dB PAE, Max is 34.3% PAE@12dB Pin back-off is12.2%.