完整後設資料紀錄
DC 欄位語言
dc.contributor.author黃健軒en_US
dc.contributor.authorHuang, Chien-Hsuanen_US
dc.contributor.author陳巍仁en_US
dc.contributor.authorChen, Wei-Zenen_US
dc.date.accessioned2014-12-12T01:37:34Z-
dc.date.available2014-12-12T01:37:34Z-
dc.date.issued2011en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT079711631en_US
dc.identifier.urihttp://hdl.handle.net/11536/44331-
dc.description.abstract本論文提出一個10GHz寬頻之全數位式非整數鎖相迴路。其中,在不使用多模除頻器(Multi-Mode Divider)的情況下,將二位元相位輸出負回授至參考相位與相位誤差處,使相位偵測器行為如同和差調變器,藉此達到非整數鎖相的功能,並降低參考相位雜訊與量化雜訊對輸出的影響。利用此機制在模擬中的頻寬可達4MHz。此論文中,並提出一個輸出平均為零的擬隨機二進位序列(PRBS)電路,使其達到小數的鎖定時,亦可降低突波的影響。此論文中的晶片是使用90nm CMOS技術實現,整體晶片面積為1.082mm2,使用電壓為1V,消耗功率約9.4 mW。zh_TW
dc.description.abstractA 10 GHz, wideband fractional-N all digital PLL. Without the helping of a multi-mode divider, the fractional phase locking function is achieved by negative feedback from binary PD output to reference accumulator and phase error accumulator. The behavior of phase detector is just like delta-sigma modulator. In this mechanism, the bandwidth of PLL is broad to 4MHz. When PLL is lock, a dithering with zero mean output voltage reduce spur effect. Implemented in a 90 nm CMOS technology, the chip size including bonding pad is 1.082mm2. The ADPLL core consumes 9.4 mW from a 1V supply.en_US
dc.language.isozh_TWen_US
dc.subject全數位鎖相迴路zh_TW
dc.subject非整數頻率鎖相迴路zh_TW
dc.subject寬頻zh_TW
dc.subjectAll-Digital PLLen_US
dc.subjectFractional-N PLLen_US
dc.subjectWidebanden_US
dc.title一個10GHz寬頻之全數位式非整數鎖相迴路zh_TW
dc.titleA 10GHz, Wideband Fractional-N All-Digital PLLen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
顯示於類別:畢業論文