應用於三維可程式化閘陣列之熱感知擺放演算法

Abstract

對於繼續遵循摩爾定律(Moore’s Law)來說三維積體電路是一個有吸引力的方法。然而在其研究中溫度問題是一個關鍵的挑戰。精確的溫度分析十分耗時，因此很難整合進擺放階段(placement)做分析。在三維積體電路研究中，有一個趨勢著重在可程式化閘陣列(FPGA)上，因為其可以同時達到複雜電路設計及上市時機縮短兩個目的，同樣的，在三維可程式化閘陣列中溫度問題也是重要的。因此，這篇論文提出兩個熱感知擺放演算法，即標準差法(Standard Deviation)和踩地雷法(Minesweeper)，皆以分散區塊分布來降低熱點(hotspot)的產生。標準差法是先去計算晶片上不同區域的使用率，再去降低數值之間的標準差，踩地雷的方法則是減少每塊區塊周圍的擁擠程度，使其均勻分布。實驗結果顯示，在可接受的線長與延遲增加下，兩方法平均可以降低9%的最高溫度、81%的溫度標準差和67%的最大溫度梯度，更甚之，踩地雷法只多增加3.49%時間就可達到目的。我們方法可有效把溫度問題整合入擺放階段同時線長跟延遲結果一樣好。

Three-dimensional (3D) integration is an attractive way to continue sustaining Moore’s Law; however, it has a critical challenge – the thermal issue. Precise thermal analysis is time-consuming and thus it is impractical to be integrated into the placement process directly for the exploding problem size in 3D technology. In 3D ICs, one of the current trends is employing field programmable gate arrays (FPGAs) because 3D FPGAs can both integrate complex circuit designs and speed up time-to-market. Since 3D FPGAs are a type of 3D ICs, thermal issue is also important for them. In this thesis, two thermal-aware placement methods for 3D FPGAs are proposed – Standard Deviation (SD) and Minesweeper (MS), which are devoted to disperse block distribution to avoid hotspots. SD utilizes the concept that minimizes the standard deviation of utilization for different parts on the chip; the idea of MS comes from minesweeper, which is to reduce the congestion of neighbors for every block. The experimental results show that improve more than 9% in maximum temperature, 81% in temperature deviation and 67% in maximum temperature gradient compared to thermal-unaware placement method with acceptable extra wire length and delay. Moreover, MS takes only 3.49% runtime overhead due to its simplified update steps. These two methods integrate efficiently thermal behavior into placement process while keeping the quality of the results good enough.