應用鎳矽化物與鍺於新穎結構複晶矽薄膜電晶體之研究

Abstract

此論文製作多種高效能新結構複晶矽薄膜電晶體，研究鎳矽化物與鍺在閘極工程、源極/汲極工程、通道結晶與非揮發記憶體上之應用。 首先我們提出一種新自我對準蕭特基(Schottky)位能障源極與歐姆接觸(ohmic contact)基極結構(SSOB)，我們使用不對稱p型接面源極 / n型接面汲極結構與自我對準鎳矽化物來形成蕭特基位能障源極與歐姆接觸基極結構，此結構能有效抑制複晶矽薄膜電晶體浮接基體效應(Floating-Body Effect)。和傳統複晶矽薄膜電晶體相比，實驗結果顯示此蕭特基位能障源極與歐姆接觸基極結構之複晶矽薄膜電晶體(SSOB-TFTs)具有較高的輸出阻抗(output resistance)、較少的臨界電壓變化(threshold voltage variation)、改善的次臨界特性(subthreshold characteristics)和較大的崩潰電壓(breakdown voltage)。然後我們首次成功發展出具完全自我對準鎳矽化物(fully Ni-salicided)於源極/汲極和閘極之n型通道與p型通道複晶矽薄膜電晶體(FSA-TFTs)，和傳統複晶矽薄膜電晶體相比，實驗結果顯示此完全自我對準鎳矽化物(fully Ni-salicided)於源極/汲極和閘極之n型通道與p型通道複晶矽薄膜電晶體(FSA-TFTs)具有較高的導通/關閉電流比(Ion/Ioff current ratio)、改善的次臨界特性(subthreshold characteristics)、較少的臨界電壓下降(threshold voltage roll-off)、較低的源極/汲極寄生電阻(parasitic S/D resistance)、較高的閘極電容和較大的場效應電子遷移率(field-effect mobility)。另外我們亦研究發展出新穎鎳矽化物引發橫向結晶技術於對稱式垂直通道複晶矽薄膜電晶體(NSILC-VTFTs)，兩階段的鎳矽化物引發橫向結晶技術(NSILC)包含第一階段: 爐管500oC 12小時退火和第二階段的700oC 60秒快速熱退火(RTA)，此新穎結晶技術可以加強結晶大小、改善結晶品質並抑制鎳金屬的累積污染。元件製作完全無經過氨電漿後處理，此新穎鎳矽化物引發橫向結晶技術於對稱式垂直通道複晶矽薄膜電晶體(NSILC-VTFTs)具有陡峭的次臨界擺動(subthreshold swing)和相當高的場效應電子遷移率(field-effect mobility)。 接著我們首次成功發展製作出自我對準堆疊矽/鍺T型閘極結構之複晶矽薄膜電晶體(Si / Ge T-gate TFTs)，此新結構之閘極靠源極/汲極兩邊具有較厚之閘極氧化層，此設計能有效地降低汲極的垂直與橫向電場而不需要額外的光罩、輕摻雜汲極(lightly doped drain)、間隙壁(spacer)或副閘極(sub-gate)等製程和結構。和傳統複晶矽薄膜電晶體相比，實驗結果顯示此堆疊矽/鍺T型閘極結構之複晶矽薄膜電晶體(Si / Ge T-gate TFTs)具有較低的關閉電流(off-state leakage current)、較高的導通/關閉電流比(Ion/Ioff current ratio)與較飽和的輸出特性(output characteristics)。 在論文的最後，我們成功發展製作出具鍺奈米微晶粒之非揮發複晶矽薄膜記憶體(poly-Si TFT nonvolatile Ge-NCs memories)，此鍺奈米微晶粒是利用低壓化學氣相沉積系統在370°C下直接沉積在氧化層上來完成。此外，我們應用適當的浮接基體效應(Floating-Body Effect)來提高寫入/抹除效率。實驗結果顯示此鍺奈米微晶粒之非揮發複晶矽薄膜記憶體(poly-Si TFT nonvolatile Ge-NCs memories)具有高的寫入/抹除效率、長的電荷儲存持久性、低的閘極和汲極干擾與良好的寫入/抹除忍受力。

In this thesis, applications of Ni-silicidation and Germanium in gate engineering, source/drain engineering, channel crystallization and nonvolatile memories for fabricating high performance new structures of polycrystalline silicon thin-film transistors (poly-Si TFTs) have been investigated. First, we have developed a new self-aligned Schottky barrier source and ohmic body contact (SSOB) method that can effectively suppress the floating-body effect in poly-Si TFTs. Experimental results show that the SSOB-TFTs give higher output resistance, less threshold voltage variation, improved subthreshold characteristics, and larger breakdown voltage compared with conventional TFTs. Second, the n-channel and p-channel fully Ni-self-aligned silicided (fully Ni-salicided) source/drain and gate poly-Si TFTs (n-channel and p-channel FSA-TFTs) have been successfully are successfully developed and fabricated for the first time. Experimental results show that the FSA-TFTs give increased Ion/Ioff current ratio, improved subthreshold characteristics, less threshold voltage roll-off, low parasitic S/D resistance, high gate capacitance and larger field-effect mobility compared with conventional TFTs. Next, the novel symmetric vertical channel poly-Si TFTs fabricated by Ni-silicide induced lateral crystallization technology (NSILC-VTFTs) are successfully developed and demonstrated. Two step NSILC (1th step: 500oC, 12hr and 2th step: RTA 700oC, 60-sec; without NH3 plasma treatment) has been introduced to enhance the grain size and improve the crystal integrity through secondary crystallization. The NSILC-VTFTs after two step NSILC treatment show a steep subthreshold swing (S.S.) of 180 mV / dec and max field effect mobility μ= 553 cm2 / V-s with Leff = 0.6□m and gate oxide = 500Å. Then, we have successfully developed and fabricated the self-aligned Si / Ge T-gate poly-Si thin-film transistors (Si / Ge T-gate TFTs) with a thick gate oxide at the gate edges near the source and drain for the first time. The thick gate oxide at the gate edges effectively reduces the drain vertical and lateral electric fields without additional mask, lightly doped drain (LDD), spacer, or sub-gate bias. Experimental results show that the Si / Ge T-gate TFTs have low OFF-state leakage currents, improved Ion / Ioff current ratio, and more saturated output characteristics compared with conventional TFTs. Finally, we have successfully developed and fabricated the poly-Si thin-film transistor (poly-Si TFT) nonvolatile Ge nanocrystals (Ge-NCs) memories for the first time. The pure Ge-NCs trapping layer was directly deposited by low-pressure chemical vapor deposition (LPCVD) at 370°C. In addition, a programming/erasing scheme adopting appropriate floating body effect was proposed. Results show that the new poly-Si TFT nonvolatile Ge-NCs memories have high programming/erasing efficiency, long charge retention time, less gate and drain disturbance, and good endurance characteristics.