銅導線中電遷移效應所引發之故障特性探討

Abstract

隨著製程線寬快速縮小到奈米(sub-100nm)尺度時，後段連線系統中傳遞的時間延遲(簡稱為 RC 延遲)已逐漸變成限制元件效能的主要因素。因此，為了降低阻值和介電值，工業界已將金屬導線製程中所使用的材質，從鋁(銅)/氧化層變成較低阻值的銅和較低介電係數的低介電材料。然而，銅導線依舊需要解決電遷移所產生元件壽命失效機制的可靠度問題。快速地縮小銅導線的寬度，同時又要維持高的電流承受能力，和更嚴格的可靠度標準需求，電遷移效應將變成未來在銅製程中非常嚴峻的挑戰。

本篇論文將針對銅導線中電遷移效應所引發之故障機制的可靠性問題做一系列的探討。第一章簡介電遷移的物理機制，第二章詳述實驗技巧和樣本準備流程，第三章首先使用銅導線製程中不同的低介電值材料和不同的測試結構互相比較其電遷移效應。不同的測試結構設計可以用來作故障模式分析，進而找出連線系統中的弱連結，三層且兩端使用via 作連結的金屬線發現到電遷移壽命和所加的電流方向有很大的關係，再者，不同製程策略流程會導致不同的電遷移結果及其故障模式。多重電遷移故障模式在銅雙鑲嵌式製程中已被完整地研究。利用重疊和弱連結模型的統計方法可以決定每一個故障模式的壽命，另外，根據阻值對時間變化關係圖，可以找出其對應的故障模式的壽命。兩種方法得到非常一致的結果。

接下來第四章，瞭解到連線系統中的弱連結，根據這資訊，一個很適合研究銅導線和蓋層之間接面特性的電遷移結構被設計出來。藉著修改蓋層沉積之前的清洗步驟和改變銅蓋層材料的方法，對電遷移壽命有相當顯著的改善。吾人提出一個可能的機制來解釋這個電遷移壽命提高原因，並發現到蓋層沉積前產生銅矽化合物(Cu-silicide)和銅/蓋層之間介面的黏著力對電遷移可靠度有非常重要的影響，且銅/蓋層之間介面的黏著力可以直接關聯到其壽命和活化能。

第五章接著研究電遷移在不同寬度從0.12到10微米和不同管洞/線(via/line)的排列變化。線寬縮小對電遷移壽命變化有兩方面不同的現象，第一是線寬小於1微米時，電遷移中位數故障時間(MTF)隨著線寬只有些微的變化，除了因為via 限制的條件。第二是線寬大於1微米時，在這區域 MTF和線寬有著強烈的關聯。吾人提出一個可能的理論來解釋這個電遷移壽命趨勢，對多晶結構的金屬線(寬度大於1微米)，最主要擴散路徑是晶粒邊界和表面擴散。對於線寬大於1微米時，主要的晶粒邊界擴散的活化能大約比起表面和晶粒邊界擴散的活化能高0.2 eV。使用在電遷移下銅移動速度，亦可得到其相對的活化能，其結果與量測值相當一致。在銅連線系統中，控制電遷移壽命的機制已被完整地研究，進而可以藉著巧妙設計via 連線而達到最常的壽命。

第六章，利用不同金屬線長度的結構，不同的電流密度和更接近真實情況的三層結構，吾人對電遷移中的短線長度效應作一系列完整的研究，銅製程已被良好的開發，確保缺陷不會造成影響。使用壽命量測和阻值劣化隨時間變化的關係來描述這現象。吾人提出一個簡單的模型理論來解釋不同長度和電流組合時的電遷移壽命趨勢，結果指出臨界長度值(jL)c和溫度相關，在250和300度C 區間隨著溫度下降而上升，藉著一系列電遷移實驗可以得到非常多深刻的理解，更可層別出銅鑲嵌技術其電遷移的特殊行為。

最後於第七章，總結本論文的結論，並對未來研究方向提供一些建議。此研究針對銅導線中電遷移效應所引發之故障機制的可靠性問題做一系列的探討。從設計測試電遷移結構，找出銅鑲嵌製程在連線中最弱的部分，接著，利用製程改變找出提高銅電遷壽命的方法，並提出模型解釋。最後，改變銅導線的幾何寬度、長度和不同via/line結構作一系列研究，實驗結果可由吾人的理論解釋，並提供給設計者對於電遷移可靠度設計的規範。藉著這一系列電遷移實驗可以得到非常多深刻的理解，更可層別出銅鑲嵌技術其電遷移的特殊行為。

The back-end-of-line (BEOL) RC delay has gradually become a major limiting factor in circuit performance as a result of the rapid shrinking of critical dimensions. With reduced resistivities and dielectric constants, the metallization system for the interconnect structures has shifted from Al(Cu)/oxide to copper/low-k dielectrics. However, Cu interconnects still pose a reliability concern due to electromigration-induced failure over time. The rapid decrease in Cu conductor dimensions while maintaining a high current capability and a high reliability has emerged as a serious challenge.

The objective of this dissertation is to investigate the characteristics and failure mechanism involved in Cu electromigration. Chapter 1 gives an introduction to the topic and discusses the background to study. Chapter 2 describes electromigration testing and analysis techniques in detail, and is intended to help familiarize the reader with the experimental aspects of this work in order to create a basis of understanding for the results sections that follow. In Chapter 3, first of all, Cu interconnect electromigration is examined using three low-k materials (k= 2.65 ~ 3.6) in a variety of structures. A number of test structures were designed to identify the EM failure modes and the weak links in the interconnect system. A strong dependence on current direction in the electromigration lifetime of three-level via-terminated metal lines was shown. Moreover, individual processing approaches lead to distinct EM behaviors and related failure modes. Multimodality in the electromigration behavior of Cu dual-damascene interconnects was studied. Both superposition and weak-link models were used for the statistical determination of the lifetimes of each failure model (statistical method). Results correlated to the lifetimes of the respective failure models physically identified according to resistance time evolution behavior (physical method). A excellent agreement was achieved.

Based on the above understanding, the weak links of interconnect system were identified.Chapter 4 describes the correlation between the electromigration lifetime and the Cu surface cap-layer process. An especially suitable EM test structure was designed to evaluate the properties of the Cu cap-layer interface. A significant improvement in electromigration lifetime is achieved through modification of the pre-clean step before the deposition of the cap-layer and by changing the Cu cap/dielectric materials. A possible mechanism for the enhancement of EM lifetime was proposed. A Cu-silicide formation prior to cap-layer deposition and the adhesion of the Cu/cap interface were found to be the critical factors in controlling Cu electromigration reliability. The adhesion of the Cu/cap interface can be directly correlated to the electromigration MTF and the activation energy.

Chapter 5 outlines the effects of width scaling and layout variation on dual-damascene Cu interconnect electromigration. Electromigration versus line width in the 0.12—10 um range and the configuration of the via/line contact has been investigated. There are two scenarios that cover the impact of width scaling on electromigration. One is the width <1 um region, in which the MTF shows a weak width dependence, except under the via-limited conditions. The other is the width >1 um region, in which the MTF shows a strong width dependence. A theory was proposed to explain the observed behavior. For polycrystalline lines (width >1 um), the dominant diffusion paths are a mixture of grain boundary and surface diffusion. The activation energy for the dominant grain boundary transport (width >1 um) is approximately 0.2 eV higher than that of the surface and grain-boundary transport (width ~ 1 um). The derived activation energies for both grain-boundary and surface diffusion are obtained from the Cu drift velocity under EM stressing. The activation energy data obtained from both the measured and derived methods for both the surface and grain-boundary transport were found to be compatible. The mechanisms governing the EM lifetime of interconnects leads to the identification of via interconnect design rules for maximizing electromigration lifetime.

In Chapter 6, the electromigration short-length effect is investigated through experiments on lines of various lengths (L), being stressed at a variety of current densities (j), and using a technologically realistic three-level structure. This investigation represents a complete study of the short-length effect following the development of an enhanced dual-damascene Cu process. Lifetime measurement and resistance degradation as a function of time were used to describe this phenomenon. A simplified equation is proposed to analyze the experimental data from various combinations of current density and line length at a certain temperature. The resulting threshold–length product (jL)C value appears to be temperature dependent, decreasing with an increase in temperature in a range of 250oC to 300oC.

Finally, Chapter 7 summarizes the results of the study and outlines some potential future directions for research into the interconnect electromigration reliability field. The multimodality distributions in various Cu/low-k processes are fitted using various bimodal methods to obtain precise lifetime values. Methods of optimizing the Cu electromigration performance have been investigated through Cap/dielectric interface re-engineering. Geometric variations of the test structure, including width scaling, length scaling, and vai/line configuration effects, were investigated to reveal the characteristics of Cu electromigration. A possible model is proposed to explain the electromigration behavior, and provides the means to ensure future design-in reliability. Much insight into electromigration failure modes and characteristics has been gained through experimentation using Cu dual-damascene technology to identify its distinctive behaviors.