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dc.contributor.author許勝福en_US
dc.contributor.authorSheng-Fu Hsuen_US
dc.contributor.author柯明道en_US
dc.date.accessioned2014-12-12T01:37:39Z-
dc.date.available2014-12-12T01:37:39Z-
dc.date.issued2005en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT009111811en_US
dc.identifier.urihttp://hdl.handle.net/11536/44368-
dc.description.abstract本論文將針對由系統層級靜電放電測試所引發的暫態觸發閂鎖效應進行研究分析。主要的研究方向包括：(1)了解造成此暫態觸發閂鎖效應的物理機制，(2)發展相關的元件層級(Component-Level)實驗設置，(3)評估各種面板層級(Board-Level)雜訊濾波器對抑制暫態觸發閂鎖效應的效用，以及(4)暫態觸發閂鎖效應相對於積體電路電源腳位上雜訊電壓之阻尼頻率(Damping Frequency)及阻尼因子(Damping Factor)的關係。除了上述有關暫態觸發閂鎖效應的研究主題外，由於高電壓(High Voltage, HV)互補式金氧半場效電晶體製程中的閂鎖效應一直以來受到工業界所重視。因此本論文也將針對高電壓互補式金氧半場效電晶體製程，研究各種不同的高壓元件結構對閂鎖效應敏感度的影響。zh_TW
dc.language.isoen_USen_US
dc.subject閂鎖效應zh_TW
dc.subject系統層級靜電放電zh_TW
dc.subjectLatchupen_US
dc.subjectSystem-Level ESD Testen_US
dc.title系統層級靜電放電測試下之積體電路暫態觸發閂鎖效應zh_TW
dc.titleTRANSIENT-INDUCED LATCHUP IN CMOS INTEGRATED CIRCUITS UNDER SYSTEM-LEVEL ESD TESTen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
Appears in Collections:Thesis


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