時脈樹和正反器重新散布之共同合成方法

Abstract

在這篇論文中，我們提出了一種優化方法為使用自下而上的群聚 的正反器來降低功耗以及將信號線長最小化。比較以往對於減少正反 器的研究，我們的方法能達到在正反器的功耗和減少信號線長之間的 最佳優化。我們所提出的方法在正反器的功耗和減少信號線長方面優 於[3]和[14]。與[8]比較，我們的方法可以減少 15.8%的信號線長以及 增加 1.8%的正反器功耗。由於自下而上群聚方式的特性，我們提出 的方法對於初始配置能夠達到最小的擾動。 我們進一步改善我們的方法，結合時鐘樹合成，利用 K -means 分 群法識別正反器的群集和更換正反器處於最佳時鐘樹的位置，這樣可 以減少功耗。實驗結果表明，我們的交錯機制可以達到最佳的時鐘樹 功耗。 我們從所有以前出版的著作[3] [14] [8]獲得執行檔和評估執行結 果使用完全相同的參數。正反器的最終位置轉換為 ISPD2010 標準格 式[13]以及使用 NGSPICE[1]評估最後的時鐘樹合成結果。

In this thesis, we propose an optimization methodology using agglomerative clustering for flip-flop’s power reduction and signal wirelength minimization. Comparing to previous works on flip-flop reduction, our method can reach the best optimization between flip-flop’s power and signal wirelength reduction. Our proposed methodol- ogy outperforms [3] and [14] in both flip-flop’s power and signal wirelength reduction. Comparing with [8], our methodology can reduce signal wirelength by 15.8%with 1.8% increase in flip-flop power consumption. Due to the nature of agglomerative clustering, our proposed method also creates least perturbation to original placement.

We further improve our method by integrating with clock tree synthesis using k-means clustering to identify cluster of flip-flop and replace flip-flop in an optimal location such that clock tree power consumption can be reduced. Experimental result demonstrates that our interleaving mechanism can reach the best clock tree power consumption.

We obtained binaries from all of the previous published works[3][14][8] and evaluate them using exact same parameter. The final location of flip-flop is converted to ISPD 2010 benchmark format[13] and final result of clock tree synthesis is evaluated using NGSPICE[1].