利用矽控整流器當做記憶單元之系統層級靜電放電暫態偵測電路

Abstract

靜電放電 (Electrostatic Discharge, ESD) 是造成電子產品遭受過度電性應力(Electrical Overstress, EOS) 最主要的原因。近年來，隨著積體電路 (Integrated Circuits, ICs) 技術進步至深次微米製程，同時為了減少電子產品成本，越來越多的積體電路整合在單一晶片系統上。在先進製程中，較薄的氧化物層和較窄的通道，都會使得積體電路的產品更容易受到靜電放電的破壞，因此，靜電放電的防護設計在積體電路技術中是一項很重要可靠度議題。 系統層級靜電放電在近年中的可靠度問題逐漸受到重視。許多電子產品即使已經通過元件層級靜電放電(Component-Level ESD)規範的測試，仍然無法達到系統層級靜電放電(System-Level ESD)防護的要求。在系統層級靜電放電防護的測試條件下，快速暫態雜訊會使得系統進入未知的當機、故障，或是不正常的工作狀態。傳統的解決方法是在微電子產品之中，加入許多種不同的濾波或是抗雜訊用的分離元件，但卻大幅地增加了微電子產品的生產成本。因此，對於系統層級靜電放電防護而言，應用於金氧半導體製程的積體電路設計防護方法可以整合於晶片系統中，減少產品成本，更具有其重要性。 本論文首先利用矽控整流器(Silicon Controlled Rectifier, SCR)元件會被暫態突波觸發的特性，提出了一種應用於系統層級靜電放電防護的暫態偵測電路設計。電路主要的原理是利用矽控整流器當作記憶元件。由實驗的結果證實，當有系統層級靜電放電事件發生時，提出的電路可以成功的偵測並且記憶快速暫態電波在積體電路電源線上產生的干擾現象。 其次，提出一個結合積體電路雜訊濾波器以及暫態偵測電路的四位元暫態對數位轉換器。利用電流鏡電路，可以放大在電源線之間的等效電容值，在雜訊濾波器上的電容值可以有效的減小並節省晶片面積，以及避免漏電問題。此轉換器可以成功的將系統層級靜電放電之電壓轉換為四位元數位碼輸出，因此能夠確切知道積體電路在系統層級靜電放電測試之下所遭受影響之程度。 這份論文總共分成五個章節。第一章是有關於系統層級靜電放電防護國際法規的內容和條例；第二章介紹了傳統用來解決系統層級靜電放電防護的方法；第三章為以矽控整流器做為記憶單元的暫態偵測電路之介紹及實驗結果；第四章提出四位元暫態對數位轉換器，包括模擬和量測結果；第五章為此份論文的結論和未來展望。

Electrostatic discharge (ESD) is the main reason that causes electrical overstress (EOS) on microelectronic products. Recently, as technology scaling down to the deep sub-micron, more integrated circuits are integrated into single chip to decrease the cost of microelectronic products. Due to thinner oxide and shallower junction depth in advance technology, microelectronic products equipped with CMOS ICs are more susceptible to ESD damage. Therefore, ESD protection has become an important reliability issue in CMOS ICs. System-level ESD tests is an increasingly important reliability issue for CMOS ICs. It has been reported that reliability issues still exist in CMOS ICs under system-level ESD tests, even though they have passed component-level ESD specifications. The transient noise generated by system-level ESD events can cause microelectronic system into locked state, frozen state, or even hardware damage such as transient-induced latch-up. For traditional solutions, extra discrete components are often added on printed circuit board (PCB) to suppress system-level ESD events in microelectronic products. However, those discrete components are substantially increasing the cost of microelectronic products. As a result, chip-level solutions with silicon integration and to meet high system-level ESD specification for microelectronic products are strongly requested by IC industry. In this thesis, first, with silicon controlled rectifier (SCR) device as memory unit, on-chip SCR-based transient detection circuit has been proposed and fabricated in 180nm CMOS process. It has been investigated that, under system-level ESD tests, the SCR device can be triggered on and the cross voltage can be dropped into holding voltage. Experimental results has confirmed that, when system-level ESD events happens, the detection circuit can successfully detect and memorize the occurrence of positive and negative fast electrical transients coupled on the power line and ground line of CMOS ICs. Furthermore, with hardware/firmware system co-design, display panel can automatically recover from the frozen state into normal operation after the system-level ESD zapping. Second, a new on-chip transient-to-digital converter composed of four CR-based transient detection circuits and four different noise filters has been successfully designed and verified in a 130nm CMOS process with 1.8-V devices. By using the current amplification techniques, capacitor used in the noise filter could be reduced to save silicon area and avoid leakage in deep submicron process. The output digital codes of the proposed on-chip transient-to-digital converter correspond to different level of positive/negative ESD voltages under system-level ESD tests. And these digital codes can be used as the firmware index to execute partial/total auto-recovery procedures in microelectronic systems. This thesis is divided into five parts. In the first chapter, international standards about system-level ESD are generally guided. In chapter two, some traditional solutions to overcome system-level ESD events are collected and introduced. In chapter three, on-chip SCR-based transient detection circuit is proposed. In chapter four, on-chip transient-to-digital converter has been simulated in detail and circuit performance has been verified under system-level ESD tests. The last chapter includes conclusions and future works.