以電流模式操作之低功率和高速率的靜態隨機存取記憶體

Abstract

本論文主要針對低功率消耗的靜態隨機存取記憶體的設計與分析。靜態隨機存取記憶體的存取路徑可分為三部分:一為寫入路徑，從位元址輸入到列位元線端;另一為讀取路徑，從列位元線到資料輸出端;最後為記憶細胞元。 藍達雙極性電晶體是利用金氧半場效電晶體與其寄生的雙極性電晶體所合成的一種電壓控制負微分電阻電晶體，可應用於記憶的元件。本文提出新的藍達雙極性電晶體結構，並以簡單的電路模式與元件物理來探討其工作原理。利用所提的藍達雙極性電晶體，設計完成新型單邊讀寫記憶細胞元。 設計一個低功率且高效能的靜態隨機存取記憶體，常常著重於減少工作時的工率及被用狀態的直流電流與漏電流。為減少讀寫操作時所消耗的功率，我們提出電流模式讀寫操作的機制以取代傳統的電壓模式。本論文提出電流模式操作感測放大器，當位元線的電壓僅需少許的變化，此感測放大器便能順利的讀取，並且能降低雜訊。另外，提出以電流模式操作的寫入驅動器，其寫入時僅需將位元線的電壓作少許的變化，不僅可降低功率的消耗並可加速寫入的動作。利用電流模式的讀寫技術，讀取速度與寫入的脈衝寬度幾乎與位元線和資料元線的電容負載無關。根據此電流模式，提出一個可操作於高速低功率的細胞元。此細胞元的存取電晶體和反向器電晶體的尺寸幾乎相同，並可經由位元線的微小電壓差而驅動。 為評估此電流模式技術，使用0.35微米一層複晶矽兩層金屬製程，製作一個32Kx8的靜態隨機存取記憶體。此記憶體在3伏特供壓下其存取時間為9奈秒，動態電流在100百萬赫茲頻率工作時為28毫安培。

This thesis explores the design and analysis of Static Random Access Memories (SRAMs) and focuses on low power operation. The SRAM access path is split into three portions: from address input to word line rise (the write operation), from word line rise to data output (the read path) and memory cell. The techniques to optimize both of these paths are investigated. The voltage-controlled negative-differential-resistance device by using a merged integrated circuit of n-channel MOSFET and parasitic NPN bipolar transistor, called Lambda bipolar transistor (LBT), is known for its memory application. In this thesis, a new LBT structure is developed and its characteristics are derived by simple circuit model and device physics. A novel single-sided memory cell based on the proposed LBT’s is presented. High performance and low power SRAM design always focuses on reducing dynamic power dissipation at the operating state and decreasing DC current and leakage current at the standby state. To reduce operation power without decreasing read/write speed, we propose special current-mode read/write mechanism instead of conventional voltage-mode circuits. In this thesis, a new current-mode sense amplifier is proposed to sense the bit-line signal even though the voltage swing of the bit-line is small, and the non-floating design reduces noise produced during sensing in the standby mode. The current-mode write driver can reduce the bit-line swing when data write in, not only decreasing power consumption but also speeding up writing access time. Using new current-mode techniques for read and write operation, the sensing speed and write pulse width are insensitive to the bit-line and data-line capacitances and a separated positive feedback technique is used to enable the circuit to operate at high-speed and low-power. These techniques always keep the voltage swing of the bit-line and data-line quite small. Based on current-mode operation, a memory cell that operates at low-power current-mode is developed. The memory cell has almost equally sized access and inverter transistors, which can be toggled using a small differential bit-line voltage. The presented techniques were demonstrated to be useful by evaluating an experimental 32Kx8 SRAM chip using 0.35um 1P2M CMOS process technology. An experimental 32Kx8 CMOS SRAM with a 9ns access time at a supply voltage of 3V is described to evaluate the new current-mode techniques. The active current is 28mA at 100MHz and 25℃.