應用於心跳節律器之低電壓低功率三角積分調變器

Abstract

近年來低功率低電壓之混和訊號電路設計技巧為市場提供了多種類之可攜式，植入式裝置。其中低功率消耗及小尺寸為其最主要的規格。故在未來之發展上，低電壓之設計將成為不可避免的趨勢。 在此論文中，提出一個應用於心跳節律器之低功率與低電壓的三角積分調變器。使用反相器放大器做為電容切換式積分器中的運算放大器及低失真架構，用以實現一個二階的三角積分調變器。而以反向器放大器做為運算放大器可以有效降低三角積焚調變器之消耗功率。為了降低製程偏移的影響，使用偏移電壓補償之技巧，用以消除積分器中運算放大器的偏移電壓。由於低電壓的系統設計，會使得切換的開關無法正常的導通，另外將使用拔薛帶式開關去解決低壓下訊號傳導的問題。 所提出的低功率低電壓三角積調變器將被實現在TSMC 0.18μm CMOS的製程，其晶片面積為0.71×0.59 mm2 (不含PAD)，當取樣頻率在25.6kHz、頻寬被設定在100Hz及電壓0.4V時，由量測結果可知最大之訊號失真雜訊比(SNDR)為47.68dB，動態範圍(DR)為68.7dB。整個晶片之功率消耗僅僅只有326nW。

In recent years, low power low voltage mixed-signal circuit design technologies have brought a considerable variety of portable, implantable battery-powered devices to the market. Due to the battery-operated and implantable specification, low power consumption and small physical size are the primary importance. Therefore, the low voltage circuit design is an inevitable trend for the future. This thesis proposes a low power, low voltage Delta-Sigma Modulator (DSM) for pacemaker front-end circuits. In our design, a low-distortion architecture is used. An inverter-based amplifier is used for low power consumption which is most concern in bio-medical applications. To reduce process variation, the offset compensation technique is introduced in switching procedure of the integrators. Additionally, bootstrapped S/H switches are developed for properly signal processing in ultra-low voltage condition. The proposed low-power, low-voltage DSM is operated under 25.6kHz clock rate and 100Hz input signal bandwidth with a supply voltage of 0.4V. The chip is implemented with TSMC 0.18μm CMOS technology with active die area of 0.71×0.59 mm2. As the results of measurement, the peak SNDR is 47.68dB and the dynamic range is 68.7dB. The chip consumes only 326nW.