應用於24 GHz 連續調頻雷達之0.18 μm CMOS 低雜訊放大器與混波器

Abstract

在本篇論文中，使用標準0.18 μm CMOS設計應用於24 GHz連續調頻雷達的兩個電路。第一個電路為低功率消耗、高增益的低雜訊放大器。第二個電路為低雜訊放大器與混波器的整合設計。 第一個電路包含三個部分: (1)兩個共源級電晶體採用電流再利用結構 (2) 加入中間級匹配與增益提升架構的疊接組態，以進一步提升增益 (3)為了量測考量，源級隨耦器作為輸出緩衝級。實作量測的中心頻為22.7 GHz，增益為18.95 dB，雜訊指數為5.8 dB，消耗11.3 mW的功率。輸入1-dB增益壓縮點(IP1dB)與輸入三階截止點(IIP3)分別為-26 dBm與-16.5 dBm。晶片面積為0.47 mm2。 另一個電路為LNA與混波器的整合設計。採用折疊式混波器，以提升混波器的線性度，降低對整體電路線性度的影響。模擬之轉換增益為13.2 dB，雜訊指數為4.6 dB，功率消耗為12 mW。IP1dB與IIP3分別為-25 dBm與-12.5 dBm。晶片面積為0.68 mm2。

In this thesis, two circuits are designed for 24 GHz FMCW applications in standard 0.18 μm CMOS technology. The first circuit is a low power and high gain low-noise amplifier (LNA). The second circuit is an integration of LNA and mixer. There are three parts in the first circuit: (1) a current-reusing structure including two common source transistors, (2) a cascode topology with inter-stage matching and gain-boosting designs to further increase the gain, (3) a source follower as an output buffer for measurements. The fabricated LNA has a gain of 18.95 dB and a noise figure of 5.8 dB at center frequency of 22.7 GHz, while consuming 11.3 mW. An input 1-dB compression point (IP1dB) and an input third-order intercept point (IIP3) are -26 dBm and -16.5 dBm, respectively. The chip size is 0.47 mm2. The other circuit is the integration of LNA and mixer. The folded-switching topology is adopted to increase linearity of the mixer and reduce the effects on whole circuit linearity. The simulation exhibits a gain of 13.2 dB and a noise figure of 4.6 dB, while consuming 12 mW. An IP1dB and an IIP3 are -25 dBm and -12.5 dBm, respectively. The chip size is 0.68 mm2.