2.4/5.8-GHz低功率低雜訊CMOS直接降頻接收機

Abstract

本篇論文設計並實現適用於無線個人區域網路的射頻積體電路。主要會依電路大小分成兩大部份：第一部份為前端接收電路中最重要的低雜訊放大器，實現應用於低頻及高頻之電路。第二部份則是實現出適用於ISM頻帶的接收機。 論文首先會對於低雜訊放大器架構及其低功率技作研究，針對一般疊接放大器做探究再利用TSMC 0.18-□m CMOS製程2.4-GHz&5.8-GHz具功率考量之單頻放大器，以及利用TSMC 0.13-□m CMOS製程結合雙變壓器元件實現雙頻帶放大器，最後利用TSMC 90-nm CMOS製程應用雙閘極技術完成60-GHz放大器。 有前章具功率考量放大器實作後，進一步延伸到低功率接收機設計。先行探討主動混頻器及可調增益放大器各類特性，分別搭配不同本地震盪產生器，在考量電流消耗下，利用TSMC 0.18-□m CMOS製程實現出具低功率、低雜訊接收機。

In this thesis, the radios which are suitable for Wireless Personal Area Network (WPAN) applications are designed and implemented. The thesis consists of two parts. The first part focuses on the most important part in front-end circuits - Low Noise Amplifier, and implements in low & high frequency. The second part implements receivers which are suitable for ISM band applications. First, we study low noise amplifier schematics and its different low-power techniques. And then, we discuss for cascode low noise amplifier and implement 2.4-GHz & 5.8-GHz power-constrained single-band amplifier in TSMC 0.18-□m CMOS technology. Otherwise, we use trifilar-type component implementing dual-band amplifier in TSMC 0.13-□m CMOS technology. Finally, 60-GHz dual-gate LNA is implemented in TSMC 90-nm CMOS technology. Because power-constrained amplifier implemented in former chapter, we can use it to extending to the low power receivers. First , we consider various performance in active mixer and VGA. Composed with various LO generator individually , we implement low power low noise receivers on the power restriction in TSMC 0.18-□m CMOS technology.