考慮溫度效應的三維積體電路功率最佳化方法- 雙電壓分配法

Abstract

三維積體電路被視為一個有效解決二維積體電路上過長導線造成的問題之技術進而改善晶片效能。然而過高的溫度將成為三維積體電路嚴峻的挑戰並且減弱三維積體電路低功率特性的優點。因此，同時考慮溫度效應與功率最佳化是非常重要的。在這篇論文中，我們提出一個利用雙電壓源的方法來降低三維積體電路上的總功率消耗。此降低三維積體電路總功率損耗的方法: 1) 所提出的雙電壓源法同時考慮三項因子作為電壓分配的標準，包含了功率延遲敏感度(power-delay sensitivity)、群聚效應和電壓轉換器的預算；2) 利用三維度電熱模擬分析器得到此三維積體電路的溫度；3) 採用具溫度相關性之邏輯閘延遲(gate delay)模型，並且完成一套考慮溫度的時序分析。實驗的結果驗證了我們方法的有效性，並且指出在電路分析中考慮熱效應(thermal effect)是極重要的。

The three dimensional integrated circuits (3D ICs) have been viewed as an effective method to improve chip performance by overcoming the bottleneck of long interconnects in the 2D ICs. However, the higher temperature becomes a serious challenge for 3D ICs and mitigates the advantage of low power. Therefore, it is important to propose an effective method considering thermal effect and power optimization simultaneously. In this thesis, we present a methodology to minimize the total power consumption in the 3D ICs by employing a dual supply voltage technique. The proposed approach consider three main headings: 1) a voltage assignment process consider three main factor, which consists of sensitivity-based, proximity effect and level shifter budget factor, to be the voltage assignment criterion for power reduction; 2) a 3D electro-thermal simulation to get the temperature of chip; 3) a thermal aware static timing analysis to obtain the thermal-related delay of gate in the circuit. The experimental results demonstrate the effectiveness of our voltage assignment method and the thermal effect in circuit performance.