完整後設資料紀錄
DC 欄位語言
dc.contributor.author吳冠儀en_US
dc.contributor.authorWu, Kuan-Ien_US
dc.contributor.author周復芳en_US
dc.contributor.authorJou, Christina F.en_US
dc.date.accessioned2015-11-26T01:05:53Z-
dc.date.available2015-11-26T01:05:53Z-
dc.date.issued2010en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT079713623en_US
dc.identifier.urihttp://hdl.handle.net/11536/44640-
dc.description.abstract  本論文討論分為兩部分,其中各部分所提出電路之晶片製作皆由TSMC 0.18μm mixed-signal/RF CMOS 1P6M製程來實現。   第一部分為一個採用後閘極耦合 (Back-Gate Coupled)方式產生四相位輸出之電流再利用震盪器。此四相位震盪器利用雙回授機制來達成改良型自發性轉移電導匹配(Modified Spontaneous Transconductance Match, M-STM),可有效降低NMOS與PMOS因製程變異對於轉移電導匹配上的影響,而可獲得更佳的輸出振幅平衡。根據量測結果顯示:本QVCO震盪頻率為4.84 - 5.17 GHz,在供應電壓為1.3V之條件下,功率損耗約為5.04mW,相位雜訊為 -117.4 dBc/Hz @ 1MHz,而figure-of-merit (FOM)則為-184.07 dBc/Hz。   第二部分則提出一種新型的低雜訊電容耦合方式來完成注入鎖定,產生所需的四相位輸出訊號,並且利用此大訊號弦波輸出來達成尾端電流之自我偏壓切換(Self-Switching Bias),這種新型態的電容耦合與尾端電流自我偏壓切換震盪器可以同時達成低雜訊與低功率損耗的優點。根據量測結果顯示:本QVCO震盪頻率為4.83-5.30 GHz,在供應電壓為1.3V之條件下,功率損耗約為3.64mW,相位雜訊為 -125.8 dBc/Hz @ 1MHz,而figure-of-merit (FOM)則為-193.87 dBc/Hz。zh_TW
dc.description.abstract  This thesis consists of two parts. All the proposed circuits were implemented in TSMC 0.18μm mixed-signal/RF CMOS 1P6M technology.   Part I presents a back-gate coupled current-reused quadrature VCO (CR-QVCO) which use double feedback mechanism to accomplish modified spontaneous transconductance match (M-STM) technique. This method is able to eliminate the transconductance difference between NMOS and PMOS transistors so that high output amplitude balance can be achieved. According to the measured results, the oscillation frequency is 4.84 - 5.17 GHz, and the power consumption is about 5.04mW at the supply voltage of 1.3V. The phase noise at 1MHz offset is -117.4dBc/Hz and the figure-of-merit (FOM) of the proposed QVCO is about -184.07dBc/Hz.   Part II proposes a novel low noise capacitor-coupling method to perform injection locking, and therefore quadrature signals at the output can be obtained. Moreover, by using these large signal sine-wave outputs to make the tail-current transistors self-switching, the advantage of lower phase noise and lower power consumption can be simultaneously achieved. According to the measured results, the oscillation frequency is 4.83 - 5.30 GHz, and the power consumption is about 3.64mW at the supply voltage of 1.3V. The phase noise at 1MHz offset is -125.8 dBc/Hz and the figure-of-merit (FOM) of the proposed QVCO is about -193.87 dBc/Hz.en_US
dc.language.isoen_USen_US
dc.subject四相位震盪器zh_TW
dc.subject震盪器zh_TW
dc.subject電流再利用zh_TW
dc.subject低相位雜訊zh_TW
dc.subjectQVCOen_US
dc.subjectVCOen_US
dc.subjectCurrent-Reuseden_US
dc.subjectLow Phase Noiseen_US
dc.title新型低相位雜訊電流再利用四相位震盪器之設計與研究zh_TW
dc.titleDesign of the New Architecture for Low Phase Noise Current-Reused Quadrature VCOen_US
dc.typeThesisen_US
dc.contributor.department電信工程研究所zh_TW
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