隨機金屬閘極功函數導致之16奈米金氧半場效應電晶體元件及電路特性擾動之研究

Abstract

金屬閘極與高介電係數閘極絕緣材料的使用使得摩爾定律能夠延續，且已成為奈米電晶體元件開發不可或缺之重要技術。然而在製程上，金屬材料在結晶的過程中，晶格顆粒的大小與方向為一個隨機的過程，又由於金屬晶格排列的不同造成金屬表面原子數量及電偶極強度的不同，造成不同的晶格排列會有不同的表面電位，進而影響金屬的功函數值，此一功函數值的不固定，將帶來新的擾動來源。為了探討此一擾動來源的重要性以及對於奈米元件與電路特性的影響，有別於文獻中提出的有效功函數擾動分析法，本論文應用蒙地卡羅方法三維度電晶體元件模擬方式，首先將閘極金屬細分成許多的小塊，再依照不同晶格出現的機率，分別隨機地給予每一小塊相對應的功函數值，藉此模擬出閘極金屬表面晶格隨機排列的現象，並藉此廣泛的分析金屬閘極功函數擾動對於16奈米金屬閘極金氧半場效電晶體特性暨其電路之影響。 在元件特性擾動方面，本論文分析了金屬閘極功函數擾動對於元件臨界電壓，閘極電容，以及截止頻率的特性擾動，並探討了其物理機制，模擬結果發現其對於元件臨界電壓造成不可忽略的影響，研究發現不同的金屬晶格排列的大小，數量，以及位置的不同，會造成臨界電壓值的擾動，此現象藉由通道表面的電位，電荷，以及能帶的分布得以解釋。在元件閘極電容以及截止頻率的特性分析上，研究發現金屬閘極功函數擾動只會在弱反轉區造成較大的擾動，在聚集區以及強反轉區的情形下，此一擾動將會因表面電荷集中造成的屏蔽效應而被壓抑。 在電路特性擾動方面，本論文探討了金屬閘極功函數擾動對於數位電路以及類比電路的影響，在反相器電路中，發現功函數擾動對於其延遲時間以及功率消耗均有相當的特性擾動影響，其中在功率消耗中，靜態功率消耗並不是主要的功率消耗來源，但是其擾動卻是十分重要且需要考量的一項，另外，功函數擾動對於靜態隨機存取記憶體電路的靜態雜訊容限以及電流鏡電路的電流匹配均會造成嚴重特性擾動，但在高頻電路的應用中，因屏蔽效應的關係，功函數擾動對高頻動態特性卻不會造成明顯的影響，以上的研究對於電路設計及其最佳化，均有相當的助益。 總之，本論文已分析了金屬閘極功函數對於電晶體的影響，並探討了形成的原因及分析其背後的物理機制與影響。此論文結果對於電晶體擾動壓抑之推估以及下世代電晶體特性擾動分析極有貢獻。

High-k/metal gate technology has been recently recognized as the key to sub-45-nanometer transistor fabrication because of the improvement of device performance and reduction of intrinsic parameter fluctuation. However, the use of metal as the gate material introduced a new source of variation. Recently, the averaged workfunction fluctuation method was reported to estimate the fluctuation; however, the effective work-function may over- or under- estimate the variability. This thesis computationally study the work-function fluctuation on emerging high-k/metal gate devices and investigate such variation source induced characteristic fluctuation using experimental validated threedimension device simulation. In our simulation methodology, we directly partition the device gate metal material into many sub-regions according to the measurement averaged grain size, and then we randomly generate the work-function to each sub-region according to the material properties and map them into device gate for our device simulation. Both the device and circuit characteristic fluctuation are investigated. For device characteristics, the fluctuations of threshold voltage (Vth), gate capacitance (CG), cutoff frequency (fT) of complementary metal-oxide-semiconductor (CMOS) field effect transistor (FET) devices are comprehensively analyzed. The result show that WKF will induce significant Vth fluctuation which can not be neglected. However, the impacts of WKF on device AC (CG and fT) fluctuations are reduced at zero and high gate voltage due to the screening effect of inversion layer or accumulation layer of device. The implications of device variability in nanoscale transistor circuits are also advanced. The digital circuit (CMOS inverter and static random access memory (SRAM)) and analog circuit (common source amplifier and current mirror) are examined. In CMOS inverter circuit, the fluctuations of rise time, fall time, and delay time fluctuations follow the trend of Vth fluctuation. The power fluctuations consisting of dynamic power, short circuit power, and static power are estimated. The dynamic power and short circuit power are the most important power dissipation sources. However, the static power fluctuation dominates the total power fluctuation due to the exponential relationship between the leakage current and the Vth. For SRAM, static noise margin fluctuations are explored and the WKF bring significant variations. For current mirror, the circuit performance variability caused by device mismatch is also clearly shown. However, in common source amplifier, the WKF shows less impact on high frequency characteristic owing to the small gate capacitance fluctuation.It is necessary to include the WKF effects in studying digital circuit reliability; however, for high frequency applications, the influence of WKF could be neglected. In summary, we have studied the random work-function fluctuations on nano-CMOS devices and circuits variability. The result of this study is useful for the next generation CMOS circuits and systems.