高介電值氧化物應用於三五族半導體金氧半元件之研究

Abstract

當傳統半導體如矽發展至22奈米結點時將會遇到瓶頸。在眾多的替代材料中，三五族複合物因為擁有優越的特性如高的電子遷移率而備受期待，但由於三五族複合物並沒有原生氧化物的存在，以至於半導體和閘極氧化層之間的界面品質仍有待提升。高介電值氧化物能使元件擁有更高的電容值且能在較厚的物理厚度下仍能維持與二氧化矽相同的平均氧化層厚度；其能減少漏電流並進一步提升元件特性，因此高介電值氧化物做為閘極氧化層應用在三五族複合物半導體上的金氧半元件一直是三五族複合物半導體主要的研究方向。 本實驗中將二氧化鉿及二氧化鈰加上二氧化鉿的閘極堆疊結構做為閘極氧化層沉積在砷化銦鎵上，製作成金氧半結構的電容，接著在不同的快速退火溫度後進行量測與討論;獲得極低的表面捕獲能帶以及磁滯現象。以二氧化鈰加上二氧化鉿的堆疊結構做為閘極氧化層的金氧半場效電晶體的量測結果也將被討論。

III-V semiconductor material has been researched and considered as the alternative channel material to silicon for complementary Metal-Oxide-Semiconductor (CMOS) applications beyond the 22nm node due to its superior properties. High-k dielectric was introduced as gate dielectrics for III-V material Metal-Oxide-Semiconductor (MOS) structure, because it can maintain the equivalent oxide thickness with thicker physical thickness resulting in the leakage current reduction and the capacitance improvement. In this study, HfO2 and CeO2 were used as gate oxides on InGaAs MOS capacitors; the both oxides have the larger dielectric constant than Al2O3 which is commonly used as gate oxide for III-V materials. HfO2/InAs MOS capacitors with varied Post Deposition Annealing (PDA) temperatures were demonstrated for the first in this study; low interface trap density and hysteresis were obtained which implies excellent interface quality. CeO2/HfO2 gate stack structure was introduced as gate dielectrics for InGaAs MOSFET; the design of the stack structure can improve the capacitance meanwhile prevent the diffusion between the oxide and the semiconductor. The MOSFET with CeO2/HfO2 gate oxide was also fabricated and the measurement results are discussed.