閘極介電層於矽通道與鍺通道金氧半場效電晶體之研究

Abstract

本論文探討閘極介電層於矽型與鍺型場校電晶體的應用。本文首先討論氮輪廓分佈(Nitrogen profile)與記憶應力記憶技術(stress memorization technique, SMT)於超薄氮氧化矽介電層於45奈米矽型場效電晶體之影響。在氮輪廓分佈於超薄氮氧化矽介電層的研究中，發現即使具有相同等效氧化層厚度的氮氧化矽介電層，其氮輪廓分佈仍會對閘極穿隧漏電流造成影響。而且閘極穿隧漏電流隨著氮輪廓分佈越傾斜而越大。另外相較於負型(n-type)場效電晶體，正型(p-type)場效電晶體增加的幅度更大。本文以WKB近似為理論基礎，建立一直接穿隧漏電流物理模型。此模型透過建立介電常數、能帶彎曲程度與有效載子穿隧質量對於氮輪廓分佈變化而得以合理解釋氮輪廓分佈對於正負型場效電晶體的影響。另外在記憶應力記憶技術於超薄氮氧化矽介電層研究中，本文發現異常的閘極漏電流因記憶應力記憶技術增加。本文利用載子分離量測法，鑑定出異常的閘極漏電流來自於載子經由閘極流向源極/汲極區。另外本文亦發現記憶應力記憶技術會導致閘極與源極/汲極的耦合電容增加的現象。實驗結果顯示高伸張應力導致源極/汲極的輕摻雜區(LDD)因而延伸與邊際閘極區域破壞，並引起異常高閘極穿隧漏電流。 在閘極介電層於鍺型場校電晶體的研究中，本文提出以高壓水方式對鍺型元件施予處理。為了清楚釐清高壓水對於鍺型元件中的各層薄膜的影響，本文逐步在二氧化矽於鍺基板研究高壓水對鍺基板的影響；在二氧化鋯於矽基板中研究高壓水對二氧化鋯的影響；最終實現高壓水對二氧化鋯於鍺基板處理。在二氧化矽於鍺基板研究中，經高壓水處理後的元件顯示出較平坦的表面特性與抑制電容-電壓中頻率發散(frequency dispersion)現象。而且本文發現以高壓水處理經高溫退火後的元件可以降低其漏電流。在二氧化鋯於矽基板的研究中，經高溫退火處理後的元件會因二氧化鋯結晶而導致漏電上升。經過高壓水處理後的元件，其閘極漏電流、電容遲滯現象(hysteresis)和等效電容厚度(capacitance-equivalent thickness, CET)明顯下降。其推斷源自於二氧化鋯中晶粒的缺陷與靠近矽基板的邊緣缺陷(border traps)經高壓水處理而被修復。最後研究高壓水對二氧化鋯於鍺基板上的影響。本研究發現以高壓水處理二氧化鋯於鍺基板的元件，可消除介於二氧化鋯和鍺基板中間層形成物-低氧化鍺(Ge suboxide)。在沉積或熱製程所形成的低氧化鍺會造成閘極漏電增加，也會使閘極控制能力下降。電子能譜儀(X-ray photoelectron spectroscopy)和高解析度場效電子顯微鏡(high-resolution transmission electron microscopy)的分析也驗證高壓水處理可以消除低氧化鍺。經研究發現此物理機制主要由於水氧化未完全氧化的氧化鋯，並其所生成的氫進一步與低氧化鍺還原成鍺。而且經高壓水處理後，二氧化鋯-鍺電容元件的閘極漏電流下降1000倍。 除此之外，本論文也在快速爐管退火製程中添加水和氫氣，並研究其對二氧化鋯於鍺基板的影響。實驗結果顯示，在適當的退火溫度下添加水與氫氣可有效地抑制低氧化鍺的生成並抑制閘極漏電流。但是當快速退火爐管製成達到500度時，氫氣會因劇烈的氧化還原反應造成鍺表面不平整，甚至出現孔洞現象。

This work focuses on characterization of thin gate dielectrics on silicon (Si) and germanium-based (Ge-based) metal-oxide-semiconductor field-effect transistor (MOSFET). First, the impacts of nitrogen profile (N profile) and stress memorization technique (SMT) on ultrathin oxynitride (SiON) for 45-nm Si-based MOSFETs application are investigated. The dependence of the gate tunneling current (JG) on N profile within an ultrathin SiON film was observed. It was found that gate tunneling current is dependent on N profile, even with equal oxide thickness and nitrogen dosage. Gate tunneling current increased with steeper N profile, and it had higher sensitivity for p-type MOSFET than n-type MOSFET. A direct tunneling model based on Wentzel-Kramers-Brillouin approximation has been proposed. The model described the influence of N profiles on gate tunneling current through local change of dielectric constant, band bending, and effective mass. Also, it reasonably explained the different JG sensitivity in n-/p-MOSFETs, a phenomenon that has not been addressed in earlier publications. Then, anomalously high gate tunneling current, induced by high tensile SMT is reported in this work. Carrier-separation measurement method shows the increased gate tunneling current is originated from the higher gate-to-source/drain tunneling current, which worsens when channel length is getting shorter. Also, the device with enhanced tensile strain exhibits 9% higher gate-to-source/drain overlapping capacitance. These data indicate the anomalously high gate tunneling current could be attributed to the high tensile strain that induces the effects of excessive lightly-doped drain-source (LDD) dopant diffusion and higher gate edge damage. The proposed inference is confirmed by channel hot electron stress. Then, high-pressure (HP) H2O treatment at low temperature (100~150 °C) has been proposed to treat Ge MOS devices. The effect of high-pressure H2O treatment on Ge MOS devices is examined step-by-step to discriminate the influence on individual layer within Ge MOS capacitor. The HP H2O treatment was respectively performed on SiO2/Ge stack for exploration of Ge substrate, on ZrO2/Si for exploration of ZrO2 thin film and finally realized on ZrO2/Ge capacitors. In the investigation of SiO2/Ge MOS devices, a smooth interfacial GeO2 layer between gate SiO2 and Ge is formed after H2O treatment, and the frequency dispersion of capacitance-voltage characteristics is also effectively alleviated. Furthermore, the electrical degradation of Ge-MOS after a post-gate dielectric annealing at 450 °C can be restored to an extent similar to the initial state. In the investigation of ZrO2/Si MOS devices, the dramatic increase of JG for ZrO2 dielectrics after rapid thermal annealing (RTA) at 500 °C was found and attributed to defective grain boundaries induced by thermal crystallization. After high-pressure H2O treatment, the hysteresis, gate leakage current and capacitance-equivalent thickness (CET) reduces in ZrO2/Si capacitor. It is inferred that the HP H2O treatment passivates the border traps in ZrO2 nearby Si substrate and defective grain boundary regions in the bulk of ZrO2. The HP H2O treatment was finally realized on the sputtered ZrO2 upon Ge substrate. This investigation demonstrates the effect of HP H2O treatment on the elimination of the interfacial germanium suboxide (GeOX) layer between ZrO2 and Ge. The formation of GeOX interlayer increases the gate leakage current and worsen the controllability of the gate during deposition or thermal cycles. X-ray photoelectron spectroscopy and high-resolution transmission electron microscopy reveal that HP H2O treatment eliminates the interfacial GeOX layer. The physical mechanism involves the oxidation of non-oxidized Zr with H2O and the reduction of GeOX by H2. Treatment with H2O reduces the gate-leakage current of a ZrO2/Ge capacitor by a factor of 1000. In the other way, the effects of H2O and H2 ambiences for RTA system on sputtered ZrO2 upon Ge substrate are reported in this work. The experimental results reveal that H2O or H2 in RTA process effectively suppress GeOX formation and release degradation of gate leakage current at appropriate process temperature. However, when the temperature of RTA treatment reaches at 500 °C, the aggressive oxidation-reduction reaction in H2 ambience cloud cause uneven surface and voids at the interface between ZrO2 and Ge substrate.