永磁式同步馬達向量控制晶片研製

Abstract

本論文以場效型可規劃邏輯陣列FPGA晶片為基礎，利用硬體描述語言VHDL系統層級模組化的設計技巧，實現永磁式同步馬達向量控制晶片的製作。晶片內整合了永磁式同步馬達向量控制架構之座標轉換、馬達位置回授檢測、正弦脈波寬度調變、速度迴路與電流迴路之比例-積分控制器等控制功能模組，並透過ALTERA Quartus II設計軟體進行模擬分析與功能驗證。同時採用了16位元有號數之 2's 補數方式設計晶片中所有硬體數位電路的資料數值運算，以提高馬達控制精確度與晶片資料數值運算解析度。

實驗系統方面，除了採用FPGA晶片為永磁式同步馬達的主要控制核心外，搭配馬達驅動週邊介面電路板的設計及其它功率級馬達硬體驅動電路的結合，完成了永磁式同步馬達晶片驅動控制系統的建構。並經由實驗數據的量測分析與控制參數的調整，而獲取系統較佳的控制效能表現。

In this thesis, a FPGA (Field Programmable Gate Array)-based Chip design is taken to implement a vector control chip conceptual core for permanent magnet synchronous motor (PMSM) drive, utilizing VHDL (Very High Speed Integrated Circuit (VHSIC) Hardware Description Language) modulation techniques and competence from a system planning level opinion. The function of the developed FPGA-base chip includes coordination transformation, position feedback decoding, sinusoidal pulse width modulation (SPWM), current-loop and speed-loop proportional-integration (PI)controller, and so on, and all the capabilities are verified by ALTERA Quartus II package software to complete and execute simulation and further analysis. Meanwhile, a 16-bit data length with Q14 and signed 2's format complement computation for all digital circuit design is applied as well for improving the accuracy of the motor control and numerical operation within this chip.

For the experimental setup and related system collocation, it is not taken into account except for the FPGA-based chip of the core concept for controlling a PMSM, peripheral interface circuit for motor drive board, and integration design for power stage circuit. As mention above, a PMSM control system has been constructed herein. Besides, it demonstrates the effectiveness of the proposed FPGA-based control system for the performance improvement for PMSM drive can be achieved by adjustment of the control parameter and measurement and analysis of experimental data.