低超取樣率多級和差類比數位轉換器在寬頻通訊系統上之研究

Abstract

隨著寬頻通訊系統的蓬勃發展，許多新的系統規格被建立，同時也增加了電路設計上的挑戰和難度。其中新一代的非對稱數位用戶迴路(ADSL2+)相較於傳統規格大幅的提高用戶的頻寬。由於頻寬大幅增加，ADSL2+可提供用戶更多的應用，如網路電視，視訊會議等等。但如此一來也增加了系統中類比數位轉換器設計的難度。此論文因此提出兩種新型寬頻和差類比數位轉換器。第一種轉換器是利用三級四階迴圈濾波器和1.5位元量化器來實現，並從系統模擬、電路設計、晶片量測完整說明闡述。第二種轉換器則是利用兩階共振器來當作迴圈濾波器，並可利用其產生之震盪模式來改善因電路不匹配所造成之動態範圍損失，並從理論分析、系統模擬、電路設計上做深入探討。 本論文中提出之兩種寬頻和差類比數位轉換器在與相關國際期刊文獻比較之後發現在功率消耗及解析度上確實有較佳的表現。其中第一種已成功的應用於新一代的非對稱數位用戶迴路上，相較於現存寬頻和差類比數位轉換器，此晶片達到極好的轉換效率。

The speed and resolution of analog-to-digital converter (ADC) must advance before the signal bandwidth and the modulation depth of digital telecommunications receivers can improve. Hence, the data rate achievable by a communications standard is inevitably linked to the performance of the ADC. Sigma-Delta ADCs have demonstrated the possibility of achieving very high resolutions (>13 bit) without the need for expensive post-processing techniques, such as laser trimming or calibration. Nevertheless, sigma-delta ADCs have generally a limited signal bandwidth due to their oversampling nature. The basic requirement for a broadband sigma-delta ADC is, therefore, low oversampling ratio and high sampling frequency. Among many existing architectures, continuous-time single-loop architecture, discrete-time single-loop architecture, and discrete-time cascaded architecture are three possible and popular candidates. Considering the advantages and disadvantages of each architecture, this thesis is dedicated to addresses the design of two discrete-time cascaded sigma-delta ADCs with low oversampling ratio (OSR) for broadband telecommunication applications. The first one is a low-power sigma-delta ADC for the extended bandwidth asymmetric digital subscriber line (ADSL2+); it performs 14 bit of resolution at a conversion rate of 4.4 MS/s. The core modulator employs a cascaded 2-1-1 fourth-order loopfilter with three 1.5-bit quantizers. A three-stage digital decimation filter following the modulator output is designed to accomplish the complete analog-to-digital conversion. The sampling frequency is 70.4 MHz and the signal bandwidth is 2.2 MHz, which results in an OSR of 16. The circuit is implemented in TSMC 1P5M 0.25-um CMOS technology and occupies an area of 2.8 mm2. The measured dynamic range, peak signal-to-noise ratio and peak signal-to-noise-and-distortion ratio are 86 dB, 84 dB, and 77 dB, respectively. The total power consumption is 180 mW from a 2.5-V power supply including decimation filter and reference voltage buffers. The second one is a resonator-based cascaded sigma-delta modulator (RAMSH) for low OSR applications. Based on two resonator topologies, the architecture can be immune to leakage quantization noise caused by circuit nonidealities over a large portion of the input range when OSR is low, and hence the dynamic range can be improved. The key of improving dynamic range is to use a cascade-of-resonator-with-feedforward (HQCRFF) 1-bit modulatorin the first stage and makes the modulator from normal modulation mode into a novel oscillation mode. The theoretic analysis of operational condition for oscillation mode is presented and the transient behavior between two modes is also discussed. Finally, the design methodology and simulation results of RMASH are addressed. Without using additional calibration techniques, the dynamic range of the two RMASH architectures, RMASH 2-0 and RMASH 2-2 with the op-amp dc gain of 60 dB, the capacitor mismatch of 0.2%, and the OSR of 8 can be as high as 87 dB and 84 dB respectively.