使用基於迷宮繞線法之多位元正反器合成技術降低時脈功率

Abstract

在現今的電路設計中，低功率消耗成了一個越來越重要的課題。在一個數位設計裡，如果將數個單位元正反器(one-bit flip-flop)合併成一個多位元正反器(multi-bit flip-flop)，可減少反相器的使用進而降低全部的功率消耗。另一方面，在更換了單位元正反器和多位元正反器之後，時序路徑的延遲可能會改變，從而違反了給定的時序限制。這份研究提出了一個基於迷宮繞線(maze routing-based)的多位元正反器合成技術，來儘可能的合成單位元正反器，已達到減少功率消耗的目標，同時滿足給予的時序限制和密度限制。實驗結果顯示，在合成完之後，總功率消耗可降低22%~30%，而且總繞線長度可減少原來的16%~50%。

Low-power has become an important issue for modern designs. In a digital design, the power consumption can be reduced by merging several one-bit flip-flops (FFs) into one multi-bit flip-flop (MBFF) due to the decrease of used inverters. On the other hand, the delay of a timing path may change and thus violate the given timing constraint after replacing several 1-bit FFs with a MBFF. This work proposes a maze routing-based MBFF synthesis algorithm to merge as many 1-bit FFs as possible for the objective of power minimization and simultaneously satisfy the given timing slack and density constraints. Experimental results show that after synthesis the total power consumption can be reduced by 22% ~ 30%, and the total routing length is shorter than the original designs by 16% ~ 50%.