應用於超高速傳輸正交多工分頻系統頻率域上之時間同步器

Abstract

本論文致力於研究在128-FFT下超高速傳輸正交多工分頻系統(OFDM)中，頻率域上的時間同步器，並以全數位多相位時脈管理元件(multiphase all-digital clock management)來調整取樣相位的方式補償取樣時脈誤差。 本論文所提出的演算法，利用收到封包的前端固定格式preambles，與理想preambles之間的相關性對取樣誤差(sampling phase error)與取樣時脈偏移(sampling clock offset)作估計以及補償。殘餘的取樣時脈偏移再利用後端指標追蹤 (pilot tracking)作估計並補償使取樣誤差小於 。 本論文所提出的演算法，主要應用在IEEE 所制定的無線網路標準IEEE 802.11ad，所提出頻率域上的時間同步器在高斯雜訊及多路徑衰減的環境中，以封包錯誤率(PER)小於1%為標準，效能在訊號雜訊比(SNR)失去1.4dB下可以達到容忍-300~400 ppm的時脈偏移影響。

This thesis details on the design of frequency-domain synchronizer to perform coherent sampling for 128-FFT Orthogonal Frequency Division Multiplexing (OFDM) timing recovery. The proposed algorithm focus on timing synchronization include timing acquisition, sampling clock offset (SCO) estimation and pilot tracking scheme for residual SCO. The multiphase all-digital clock management (ADCM) is utilized to adjust sampling phases estimated by timing synchronization, rather than phase-locked or delay-locked loops, and utilize the cross-correlation power between short preambles to estimation the sampling phase error and the SCO. The pilot tracking scheme tracking the gradual phase shifts caused by residual SCO and maintaining the sampling phase error < . The simulation platform is 802.11ad with TGad channel. Performances are measured under the TGad channel. At 1% PER and SCO tolerance range is -300~400-ppm, the SNR loss is only 0.8~1.4 dB in frequency-selective fading. From simulation results, the frequency-domain synchronizer has wide clock offset tolerance.