標題: | 快取分區模式效能改進的方法 Techniques to Improve the Performance of Cache Partitioning Schemes |
作者: | 戴彼德 Deayton, Peter 鍾崇斌 Chung, Chung-Ping 電機資訊國際學位學程 |
關鍵字: | 快取;shared cache |
公開日期: | 2011 |
摘要: | 當越來越多處理器共享一個快取時,會使得處理器之間對於快取資源的競爭更加劇烈,進而影響個別單一程序的效能。 快取分區方法是一個可以降低程序間互相競爭的方法,其通常將快取分割給各個處理器單獨使用,然而此方法在程序不平衡的存取快取時,會造成快取分區利用率不佳的問題。針對此問題,我們提出兩個方法做改善:1. 額外增加一塊共享分區供所有處理器共同使用2. 針對每一個處理器,給予不同的索引方式。另外,我們針對所有分區,在一般常用於減少失誤的方法下(可變動區塊大小、可變動關聯度、改變替代策略)進行討論。 As the number of processors sharing a cache increases, misses due to destructive interference amongst competing processes have an increasing impact on the individual performance of processes. Cache partitioning is a method of allocating a cache between concurrently executing processes in order to counteract the effects of this inter-process interference. However, cache partitioning methods commonly divide a shared cache into private partitions dedicated to a single processor, which can lead to underutilized portions of the cache when processes access sets in the cache non-uniformly. Two techniques are proposed designed to take advantage of this non-uniformity - the creation of an additional shared partition able to be shared amongst all processors and alternate cache set indexing functions for each core. Also discussed is the application of general miss reduction techniques (variable block size, variable associativity, and changing replacement policies) on a per-partition basis. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT079803508 http://hdl.handle.net/11536/46632 |
Appears in Collections: | Thesis |
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