單一電子在超大型積體電路元件中所造成臨界電壓擾動之三維原子量級模擬

Abstract

本篇論文是利用ISE-TCAD這套工程專用軟體來探討隨機電報雜訊(Random Telegraph Noise)在各種超大型積體電路元件中所造成的影響。我們揮別於以往的二維平均摻雜濃度的做法,導入了三維的概念。在加入隨機摻雜原子後，我們成功的模擬出單一電子在元件中特性，包含其中最具有代表性的電子繞行行為(percolation effect)。 同時我們也對單一電子在金氧半場效應電晶體中的影響隨著尺寸大小、摻雜濃度以及電子密度等參數變化做了預測。除此之外，我們也利用模擬對基極電壓以及環形佈植(Pocket Implant)對單一電子行為的影響做出解釋。 最後我們針對高介電係數的金氧半場效應電晶體以及SONOS快閃式記憶體的單一電子行為進行了模擬以及討論。發現單一電子的統計行為不會因為元件的不同而有所改變。他們都遵守電子繞行的行為。

ISE-TCAD is used to discuss random telegraph noise (RTN) on different VLSI devices in this report. We abandon the old method of 2-Dimensional uniform doping in devices and introduce a concept of 3-Dimensional “ atomistic ” doping. We successfully simulated single charge characteristic in devices, including most representative percolation behavior. We also predict single charge behavior in MOSFETs with different dimension, doping concentration and electron density. Besides, we offer explanations to the influence of bulk voltage and pocket implant on single charge behavior. At last we do a discussion on high k CMOS and SONOS flash memory with single charge behavior. We find out no matter on what devices, single charge statistical behavior is the same. They all follow percolation theory.