高壓製程靜電放電防護元件設計與其安全操作範圍之研究

Abstract

在智慧型高功率科技中，高壓電晶體已經廣泛運用於顯示器積體電路、電源供應、電源管理，和汽車電子等應用上。然而，隨著製程複雜度的提升以及工作環境日益惡化，高壓積體電路的各種可靠度議題逐漸受到重視，其重要性不容小覷。在許多可靠度的規範守則當中，靜電放電防護 (ESD) 以及安全操作範圍 (SOA) 已成為不可或缺的可靠度議題。為了減少晶片總面積，希冀設計出同時擁有穩健之靜電放電防護能力以及廣大之安全操作範圍的高壓電晶體。因此，本論文旨在探討高壓電晶體之靜電放電防護以及安全操作範圍議題。 本篇論文提出以圓形以及橢圓形之佈局方式呈現橫向擴散金屬氧化物半導體 (LDMOS) ，並實現於 0.5-□m 100-V bipolar CMOS DMOS (BCD) silicon on insulator (SOI) 製程。在許多高壓應用當中，高壓電晶體本身具備抵擋靜電放電之能力是較受歡迎的。因此本文提出於橫向擴散金屬氧化物半導體嵌入矽控整流器 (silicon controlled rectifier, SCR) 以提高靜電放電防護能力。實驗數據顯示，嵌入矽控整流器確實可有效提升靜電放電防護能力。然而，嵌入矽控整流器的相對位置安排對靜電放電防護能力有不可忽視的影響。此外，本文也探討各種佈局參數對於靜電放電防護能力的影響。 雖然嵌入矽控整流器的橫向擴散金屬氧化物半導體擁有極佳的靜電放電防護能力，但其電性安全操作範圍 (electrical SOA) 嚴重縮小，而且承受未箝制電感性切換 (unclamped inductive switch, UIS) 的能力也大幅降低。此外，本文探討未箝制電感性切換的特性，並發現若橫向擴散金屬氧化物半導體之啟動電流越大，其承受未箝制電感性切換的能力就越好，因此，在未來的未箝制電感性切換之研究中，可朝著研究其啟動電流方向努力

High-voltage (HV) transistors in smart power technologies have been extensively used for display driver integrated circuits (ICs), power supplies, power management and automotive electronics. The importance of reliability issue should not be underestimated in HV ICs as a result of the process complexity and stringent operating environments. Among the various reliability specifications, electrostatic discharge (ESD) protection and safe operating area (SOA) are becoming the essential issues for HV ICs. A HV transistor simultaneously exhibiting excellent ESD robustness and wide SOA is preferable to minimize the total chip area; hence, the aim of the thesis is to investigate the ESD performance and SOA of HV transistors. In this thesis, lateral double-diffused metal oxide semiconductor (LDMOS) with circular and elliptic layout shapes are fabricated in a 0.5-□m 100-V bipolar CMOS DMOS (BCD) silicon on insulator (SOI) process. The self-protected HV transistor against ESD stress is popular in HV applications. The insertion of silicon controlled rectifier (SCR) to LDMOS is proposed to improve the ESD robustness. Experimental results show that it can effectively improve the ESD robustness. However, the arrangement of placing embedded SCR significantly affects the ability to withstand the ESD stress. In addition, the influence of various layout parameters on ESD robustness is studied in the thesis. Though LDMOS with embedded SCR exhibits excellent ESD robustness, it suffers from a severe degradation of electrical SOA and a poor ability to withstand the unclamped inductive switch (UIS) stress. Besides, the characteristic of UIS is studied and it is discovered that a LDMOS has better ability to withstand the UIS stress when it has a higher trigger current. Engineering the trigger current of LDMOS accordingly can be a direction of future UIS studies.