直接降頻接收機適用之低雜訊放大器與限制放大器設計

Abstract

本論文的主題在於使用台積電0.25um與0.18um標準互補式金氧半製程，分別實現應用於直接降頻接收機中前置端的低雜訊放大器與解調端之前的限制放大器。利用對台積電0.25um製程之測試元件的射頻CMOS電晶體量測結果，來設計電感退化型之低雜訊放大器。所實現之晶片為低雜訊放大器串接混波器，在射頻頻率為868MHz的設計中，在500kHz之S11為-15.8dB，增益約為3dB，而10MHz之雜訊指數為19.4dB。而利用台積電0.18um製程所實現的晶片包括低雜訊放大器、兩級混波器、低通與高通濾波器，以及限制放大器。而限制放大器包含了串接增益級、直流偏移校正電路以及接收訊號強度指示器。其中，增益級是由七級相同的放大器所構成，每一級放大倍率約為11.4dB，最小輸入訊號為40uV，最大的輸出振幅固定在1.1V附近。而包含接收訊號強度指示器之限制放大器的靈敏度為-75dBm，消耗功率約為9.2mW。

These major topics of the thesis are Low Noise Amplifier（LNA） of the front-end direct conversion receiver and Limiting Amplifier in front of demodulation, and applying TSMC CMOS 0.25um and 0.18um process, respectively. Utilized the results of TSMC 0.25um process RF CMOS Testkey and design the inductive degeneration LNA. The implemented chip is composed of LNA and Mixer, and the S11 is about -15.8dB, gain is about 3dB at converting frequency 500kHz, which RF frequency is 868MHz, and the noise figure is about 19.4dB at 10MHz. Following, the implemented chip made use of TSMC 0.18um process is composed of LNA, two stages of Mixers, LHF, HPF, and Limiter. Limiter including gain stages, DC offset cancellation, and Received Signal Strength Indicator（RSSI）, where the Limiter has seven stages of the same amplifier, amplification of each stage is about 11.4dB, the minimum input signal is 40uV, and the maximum output amplitude is fixed at 1.1V nearby. Finally, the sensitivity of the Limiter including RSSI is about -75dBm, and the total power consumption is about 9.2mW.